ram.v

来自「正交信号源的单片机和cpld源码」· Verilog 代码 · 共 16 行

module ram(data,address,we,inclk,outclk,q);
input [7:0]data;
input [7:0]address;
input we,inclk,outclk;
output[7:0]q;
lpm_ram_dq myram(.q(q),
                 .data(data),
				 .address(address),
				 .we(we),
				 .inclk(inclk),
				 .outclk(outclk)
				);
defparam myram.lpm_width=8;
defparam myram.lpm_widthad=8;
defparam myram.lpm_file="map_lpm_ram.mif";//memory initialization file
endmodule