signal2.v

来自「正交信号源的单片机和cpld源码」· Verilog 代码 · 共 51 行

/*-----------------------------------------------*-
  File for  signal sourse
-*-----------------------------------------------*/
//`include"ram.v"
module signal2(reset,clk,step_value,phase_dat1,phase_dat2);
input  clk;
input reset;

input[7:0]step_value;
  
output [10:0]phase_dat1;
output [10:0]phase_dat2;

reg [7:0]step_value_store;
reg [10:0]phase_dat1;
reg [10:0]phase_dat2;
reg [10:0]phase_addr1;
reg [10:0]phase_addr2;
reg [23:0]phase_adder;                                                                                     
/******************/

/******************/

always@(posedge clk)
  begin
    if(!reset)
       begin
          step_value_store<=8'b0000_0001;
       end
    else
       begin
          step_value_store<=step_value;
       end
  end 
always@(posedge clk or negedge reset)
  begin
    if(!reset)
        begin
          phase_addr1<=11'b000_0000_0001;
          phase_addr2<=11'b000_0000_0001;
          phase_adder<=24'b0000_0000_0000_0000_0000_0000;
        end
    else
        begin
          phase_adder<=phase_adder+step_value_store;
          phase_addr1<=phase_adder[23:13]; 
          phase_addr2<=phase_adder[23:13];
        end 
  end

endmodule