signal3.v

来自「正交信号源的单片机和cpld源码」· Verilog 代码 · 共 65 行

module signal3(reset,clk,seq_ctrl,phase_addr1,phase_addr2);
input  clk;
input reset;
input[7:0]seq_ctrl;
  
output [10:0]phase_addr1;
output [10:0]phase_addr2;

reg seq_ctrl_clk;
reg [7:0]seq_ctrl_store;
reg [10:0]phase_addr1;
reg [10:0]phase_addr2;
reg [7:0]clk_div;                                                                                     
/******************/

/******************/
/*initial
  begin
  phase_adder1=24'b0000_0000_0000_0000_0000_0000;
  phase_adder2=24'b0000_0000_0000_0000_0000_0000;
  end*/
always@(posedge clk or negedge reset)
  begin
    if(!reset)
       begin
          seq_ctrl_store<=0;
       end
    else
       begin                                  //tongguo kongzhi fenpinzi(分频字） kongzhi jishu fenpin
          seq_ctrl_store<=seq_ctrl;
       end
  end 

always@(posedge clk or negedge reset)
  begin
    if(!reset)
       begin
          clk_div<=0;
          seq_ctrl_clk<=0;
       end
    else if(clk_div==seq_ctrl_store)
       begin
          clk_div<=0;
          seq_ctrl_clk<=~seq_ctrl_clk;
       end
    else
       begin
          clk_div<=clk_div+8'b0000_0001;
       end
  end

always@(posedge seq_ctrl_clk or negedge reset)
  begin
    if(!reset)
       begin
          phase_addr1<=11'b000_0000_0000;
          phase_addr2<=11'b000_0000_0000;
       end
    else
       begin
          phase_addr1<=phase_addr1+11'b000_0000_0001; 
          phase_addr2<=phase_addr2+11'b000_0000_0001;
       end 
  end
endmodule