_primary.vhd

还是一个verilog原代码,可以在modelsim下运行,强烈推荐下载

library verilog;
use verilog.vl_types.all;
entity tbsr is
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic;
        dout            : out    vl_logic
    );
end tbsr;