control.v

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· Verilog 代码 · 共 26 行

module control(clk1,cnt_for_mux,cnt,clk_488,rst,frame_clk);
output clk1;         //as the clk of mux and demux
output [4:0] cnt_for_mux;  //use cnt_for_mux to control the mux,demux
output [2:0] cnt;          //use cnt to control s_2_p;
input  clk_488,rst;
input  frame_clk;

reg [2:0] cnt;
reg [4:0] cnt_for_mux;
reg       clk1;


always@(posedge clk_488 or negedge rst or posedge frame_clk )
  if(!rst) begin
              cnt<=0;cnt_for_mux<=0;
           end
  else if(frame_clk)  begin cnt<=0;cnt_for_mux<=0;end
  else if(cnt==7)    begin cnt<=cnt+1;cnt_for_mux<=cnt_for_mux+1;end
  else cnt<=cnt+1;                              

always@(posedge clk_488)
   if(cnt==7) clk1<=1;
   else clk1<=0;        //produce clk1=8*488 
   
endmodule