s_2_p.v

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· Verilog 代码 · 共 30 行

module s_2_p(paral_data,cnt,sda,rst,clk,clk1,flag);
output [7:0] paral_data;
output flag;
input  sda,rst,clk,clk1;
input  [2:0] cnt;

reg    flag;
reg    [7:0] dabuf;
reg    [7:0] paral_data;

always@(negedge clk1 )
    paral_data<=dabuf;

always@(posedge clk or negedge rst)
   if(!rst)  begin dabuf<=0;flag<=0;end
   else 
     begin 
         case(cnt)
           3'b001: begin dabuf[7]<=sda;flag<=0;end
           3'b010: dabuf[6]<=sda;
           3'b011: dabuf[5]<=sda;
           3'b100: dabuf[4]<=sda;
           3'b101: dabuf[3]<=sda;
           3'b110: dabuf[2]<=sda;
           3'b111: dabuf[1]<=sda;
           3'b000: begin dabuf[0]<=sda;flag<=1;end
         endcase
     end
endmodule