test.v

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· Verilog 代码 · 共 54 行

`timescale 1ns/1ns
 module test;
   reg  clk,rst,frame_clk;
   reg  [7:0] d_in0,d_in1,d_in2,d_in3,d_in4,d_in5,d_in6,d_in7,d_in8,d_in9,d_in10,
              d_in11,d_in12,d_in13,d_in14,d_in15,d_in16,d_in17,d_in18,d_in19,d_in20,d_in21,
              d_in22,d_in23,d_in24,d_in25,d_in26,d_in27,d_in28,d_in29,d_in30,d_in31;
   wire [7:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
              data_out8,data_out9,data_out10,data_out11,data_out12,data_out13,data_out14,data_out15,
              data_out16,data_out17,data_out18,data_out19,data_out20,data_out21,data_out22,data_out23,
              data_out24,data_out25,data_out26,data_out27,data_out28,data_out29,data_out30,data_out31;
   wire [7:0] mux_out;
   wire [4:0] cnt1;
   wire [2:0] cnt2;
   wire       sda;
   wire [7:0] pda;
   wire       clk1;
   wire       flag;
   reg  [2:0] k;
   
   parameter  CLK_CYCLE=488;
   always     # (CLK_CYCLE/2) clk=~clk;
   
   initial  
        begin
             clk=1;rst=1;frame_clk=0;
             d_in0=7;d_in1=6;d_in2=5;d_in3=4;d_in4=3;d_in5=2;d_in6=1;d_in7=2;
             d_in8=3;d_in9=4;d_in10=5;d_in11=6;d_in12=7;d_in13=8;d_in14=9;d_in15=10;
             d_in16=11;d_in17=12;d_in18=13;d_in19=14;d_in20=15;d_in21=16;d_in22=17;d_in23=18;
             d_in24=19;d_in25=20;d_in26=21;d_in27=22;d_in28=23;d_in29=24;d_in30=25;d_in31=26;
             #(CLK_CYCLE/2) rst=0;
             # (5*CLK_CYCLE/4)   rst=1;
             for(k=0;k<=5;k=k+1)
               begin
                 #(256*CLK_CYCLE+CLK_CYCLE/4) frame_clk=1;
                 # (CLK_CYCLE/4) frame_clk=0;
                 d_in0=1+k;d_in1=2+k;d_in2=3+k;d_in3=4+k;d_in4=5+k;d_in5=6+k;d_in6=7+k;d_in7=8+k;
                 d_in8=9+k;d_in9=10+k;d_in10=11+k;d_in11=12+k;d_in12=13+k;d_in13=14+k;d_in14=15+k;d_in15=16+k;
                 d_in16=17+k;d_in17=18+k;d_in18=19+k;d_in19=20+k;d_in20=21+k;d_in21=22+k;d_in22=23+k;d_in23=24+k;
                 d_in24=25+k;d_in25=26+k;d_in26=27+k;d_in27=28+k;d_in28=29+k;d_in29=30+k;d_in30=31+k;d_in31=32+k;
               end
             #(260*CLK_CYCLE) $stop;
        end

   mux    m0(mux_out,rst,clk,cnt1,d_in0,d_in1,d_in2,d_in3,d_in4,d_in5,d_in6,d_in7,d_in8,
            d_in9,d_in10,d_in11,d_in12,d_in13,d_in14,d_in15,d_in16,d_in17,d_in18,d_in19,
            d_in20,d_in21,d_in22,d_in23,d_in24,d_in25,d_in26,d_in27,d_in28,d_in29,d_in30,d_in31);
   p_2_s  m1(sda,clk,rst,cnt2,mux_out);
   s_2_p  m2(pda,cnt2,sda,rst,clk,clk1,flag);
   demux  m3(rst,clk,clk1,flag,cnt1,pda,data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
             data_out8,data_out9,data_out10,data_out11,data_out12,data_out13,data_out14,data_out15,
             data_out16,data_out17,data_out18,data_out19,data_out20,data_out21,data_out22,data_out23,
             data_out24,data_out25,data_out26,data_out27,data_out28,data_out29,data_out30,data_out31); 
   control  m5(clk1,cnt1,cnt2,clk,rst,frame_clk);
endmodule