div_clk.rpt

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

-- Node name is '|lpm_add_sub:146|addcore:adder|:227' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_E9', type is buried 
_LC4_E9  = LCELL( _EQ041);
  _EQ041 =  i15 &  i16 &  _LC1_E20;

-- Node name is '|lpm_add_sub:146|addcore:adder|:235' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_E9', type is buried 
_LC1_E9  = LCELL( _EQ042);
  _EQ042 =  i17 &  i18 &  _LC4_E9;

-- Node name is '|lpm_add_sub:146|addcore:adder|:243' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_E4', type is buried 
_LC6_E4  = LCELL( _EQ043);
  _EQ043 =  i19 &  i20 &  _LC1_E9;

-- Node name is '|lpm_add_sub:146|addcore:adder|:251' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_E4', type is buried 
_LC2_E4  = LCELL( _EQ044);
  _EQ044 =  i21 &  i22 &  _LC6_E4;

-- Node name is '|lpm_add_sub:146|addcore:adder|:255' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_E51', type is buried 
_LC6_E51 = LCELL( _EQ045);
  _EQ045 =  i23 &  _LC2_E4;

-- Node name is '|lpm_add_sub:146|addcore:adder|:263' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_E51', type is buried 
_LC5_E51 = LCELL( _EQ046);
  _EQ046 =  i23 &  i24 &  i25 &  _LC2_E4;

-- Node name is '|lpm_add_sub:146|addcore:adder|:267' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_E51', type is buried 
_LC1_E51 = LCELL( _EQ047);
  _EQ047 =  i26 &  _LC5_E51;

-- Node name is '|lpm_add_sub:146|addcore:adder|:275' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_E46', type is buried 
_LC3_E46 = LCELL( _EQ048);
  _EQ048 =  i27 &  i28 &  _LC1_E51;

-- Node name is '|lpm_add_sub:146|addcore:adder|:279' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_E46', type is buried 
_LC6_E46 = LCELL( _EQ049);
  _EQ049 =  i29 &  _LC3_E46;

-- Node name is '~6~1' 
-- Equation name is '~6~1', location is LC3_C16, type is buried.
-- synthesized logic cell 
_LC3_C16 = LCELL( _EQ050);
  _EQ050 =  i4
         #  i5
         #  i6
         #  i7;

-- Node name is '~6~2' 
-- Equation name is '~6~2', location is LC2_E2, type is buried.
-- synthesized logic cell 
_LC2_E2  = LCELL( _EQ051);
  _EQ051 =  _LC3_C16
         #  i1
         # !i2
         #  i3;

-- Node name is '~6~3' 
-- Equation name is '~6~3', location is LC4_E4, type is buried.
-- synthesized logic cell 
_LC4_E4  = LCELL( _EQ052);
  _EQ052 =  i20
         #  i21
         #  i22
         #  i23;

-- Node name is '~6~4' 
-- Equation name is '~6~4', location is LC3_E9, type is buried.
-- synthesized logic cell 
_LC3_E9  = LCELL( _EQ053);
  _EQ053 =  i16
         #  i17
         #  i18
         #  i19;

-- Node name is '~6~5' 
-- Equation name is '~6~5', location is LC2_E9, type is buried.
-- synthesized logic cell 
_LC2_E9  = LCELL( _EQ054);
  _EQ054 =  i12
         #  i13
         #  i14
         #  i15;

-- Node name is '~6~6' 
-- Equation name is '~6~6', location is LC2_E20, type is buried.
-- synthesized logic cell 
_LC2_E20 = LCELL( _EQ055);
  _EQ055 =  i8
         #  i9
         #  i10
         #  i11;

-- Node name is '~6~7' 
-- Equation name is '~6~7', location is LC1_E4, type is buried.
-- synthesized logic cell 
_LC1_E4  = LCELL( _EQ056);
  _EQ056 =  _LC4_E4
         #  _LC3_E9
         #  _LC2_E9
         #  _LC2_E20;

-- Node name is '~6~8' 
-- Equation name is '~6~8', location is LC1_E46, type is buried.
-- synthesized logic cell 
_LC1_E46 = LCELL( _EQ057);
  _EQ057 =  i29
         #  i30
         #  i31;

-- Node name is '~6~9' 
-- Equation name is '~6~9', location is LC2_E51, type is buried.
-- synthesized logic cell 
_LC2_E51 = LCELL( _EQ058);
  _EQ058 =  i25
         #  i26
         #  i27;

-- Node name is '~6~10' 
-- Equation name is '~6~10', location is LC2_E46, type is buried.
-- synthesized logic cell 
_LC2_E46 = LCELL( _EQ059);
  _EQ059 =  i28
         #  _LC1_E46
         #  i24
         #  _LC2_E51;

-- Node name is ':6' 
-- Equation name is '_LC4_E2', type is buried 
!_LC4_E2 = _LC4_E2~NOT;
_LC4_E2~NOT = LCELL( _EQ060);
  _EQ060 =  i0
         #  _LC2_E2
         #  _LC1_E4
         #  _LC2_E46;

-- Node name is ':143' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = DFFE(!_LC6_C14, GLOBAL( clk_in),  VCC,  VCC, !_LC7_C14);

-- Node name is ':145' 
-- Equation name is '_LC7_C14', type is buried 
!_LC7_C14 = _LC7_C14~NOT;
_LC7_C14~NOT = LCELL( _EQ061);
  _EQ061 =  _LC4_E2 &  rst;



Project Information                      f:\verilog\竞赛\key_scan1\div_clk.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 117,188K