div_clk.rpt
来自「用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功」· RPT 代码 · 共 993 行 · 第 1/4 页
RPT
993 行
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk_in
78 - - - -- INPUT G ^ 0 0 0 1 rst
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\verilog\竞赛\key_scan1\div_clk.rpt
div_clk
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
148 - - A -- OUTPUT 0 1 0 0 clk_scan
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\verilog\竞赛\key_scan1\div_clk.rpt
div_clk
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - E 02 AND2 0 2 0 1 |lpm_add_sub:146|addcore:adder|:167
- 1 - E 02 AND2 0 4 0 4 |lpm_add_sub:146|addcore:adder|:175
- 2 - C 14 AND2 0 2 0 1 |lpm_add_sub:146|addcore:adder|:179
- 6 - C 16 AND2 0 4 0 4 |lpm_add_sub:146|addcore:adder|:187
- 8 - C 16 AND2 0 2 0 1 |lpm_add_sub:146|addcore:adder|:191
- 1 - C 16 AND2 0 4 0 2 |lpm_add_sub:146|addcore:adder|:199
- 6 - E 20 AND2 0 2 0 3 |lpm_add_sub:146|addcore:adder|:203
- 7 - E 20 AND2 0 3 0 3 |lpm_add_sub:146|addcore:adder|:211
- 1 - E 20 AND2 0 3 0 3 |lpm_add_sub:146|addcore:adder|:219
- 4 - E 09 AND2 0 3 0 3 |lpm_add_sub:146|addcore:adder|:227
- 1 - E 09 AND2 0 3 0 3 |lpm_add_sub:146|addcore:adder|:235
- 6 - E 04 AND2 0 3 0 3 |lpm_add_sub:146|addcore:adder|:243
- 2 - E 04 AND2 0 3 0 4 |lpm_add_sub:146|addcore:adder|:251
- 6 - E 51 AND2 0 2 0 1 |lpm_add_sub:146|addcore:adder|:255
- 5 - E 51 AND2 0 4 0 2 |lpm_add_sub:146|addcore:adder|:263
- 1 - E 51 AND2 0 2 0 3 |lpm_add_sub:146|addcore:adder|:267
- 3 - E 46 AND2 0 3 0 3 |lpm_add_sub:146|addcore:adder|:275
- 6 - E 46 AND2 0 2 0 1 |lpm_add_sub:146|addcore:adder|:279
- 3 - C 16 OR2 s 0 4 0 1 ~6~1
- 2 - E 02 OR2 s 0 4 0 1 ~6~2
- 4 - E 04 OR2 s 0 4 0 1 ~6~3
- 3 - E 09 OR2 s 0 4 0 1 ~6~4
- 2 - E 09 OR2 s 0 4 0 1 ~6~5
- 2 - E 20 OR2 s 0 4 0 1 ~6~6
- 1 - E 04 OR2 s 0 4 0 1 ~6~7
- 1 - E 46 OR2 s 0 3 0 1 ~6~8
- 2 - E 51 OR2 s 0 3 0 1 ~6~9
- 2 - E 46 OR2 s 0 4 0 1 ~6~10
- 4 - E 02 OR2 ! 0 4 0 32 :6
- 7 - E 46 DFFE + 0 3 0 1 i31 (:110)
- 5 - E 46 DFFE + 0 3 0 2 i30 (:111)
- 4 - E 46 DFFE + 0 2 0 3 i29 (:112)
- 8 - E 46 DFFE + 0 3 0 2 i28 (:113)
- 3 - C 14 DFFE + 0 2 0 3 i27 (:114)
- 8 - E 51 DFFE + 0 2 0 2 i26 (:115)
- 7 - E 51 DFFE + 0 3 0 2 i25 (:116)
- 4 - E 51 DFFE + 0 3 0 3 i24 (:117)
- 3 - E 51 DFFE + 0 2 0 4 i23 (:118)
- 8 - E 04 DFFE + 0 3 0 2 i22 (:119)
- 7 - E 04 DFFE + 0 2 0 3 i21 (:120)
- 5 - E 04 DFFE + 0 3 0 2 i20 (:121)
- 3 - E 04 DFFE + 0 2 0 3 i19 (:122)
- 7 - E 09 DFFE + 0 3 0 2 i18 (:123)
- 6 - E 09 DFFE + 0 2 0 3 i17 (:124)
- 5 - E 09 DFFE + 0 3 0 2 i16 (:125)
- 8 - E 09 DFFE + 0 2 0 3 i15 (:126)
- 3 - E 20 DFFE + 0 3 0 2 i14 (:127)
- 4 - E 20 DFFE + 0 2 0 3 i13 (:128)
- 5 - E 20 DFFE + 0 3 0 2 i12 (:129)
- 8 - E 20 DFFE + 0 2 0 3 i11 (:130)
- 1 - C 14 DFFE + 0 2 0 2 i10 (:131)
- 2 - C 16 DFFE + 0 3 0 2 i9 (:132)
- 4 - C 16 DFFE + 0 3 0 3 i8 (:133)
- 7 - C 16 DFFE + 0 2 0 4 i7 (:134)
- 5 - C 16 DFFE + 0 3 0 2 i6 (:135)
- 4 - C 14 DFFE + 0 3 0 3 i5 (:136)
- 5 - C 14 DFFE + 0 2 0 4 i4 (:137)
- 7 - E 02 DFFE + 0 3 0 2 i3 (:138)
- 5 - E 02 DFFE + 0 3 0 3 i2 (:139)
- 3 - E 02 DFFE + 0 2 0 4 i1 (:140)
- 8 - E 02 DFFE + ! 0 0 0 5 i0 (:141)
- 6 - C 14 DFFE + 0 1 1 0 :143
- 7 - C 14 AND2 ! 1 1 0 1 :145
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\verilog\竞赛\key_scan1\div_clk.rpt
div_clk
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 7/208( 3%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 23/208( 11%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog\竞赛\key_scan1\div_clk.rpt
div_clk
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 33 clk_in
Device-Specific Information: f:\verilog\竞赛\key_scan1\div_clk.rpt
div_clk
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 33 rst
Device-Specific Information: f:\verilog\竞赛\key_scan1\div_clk.rpt
div_clk
** EQUATIONS **
clk_in : INPUT;
rst : INPUT;
-- Node name is 'clk_scan'
-- Equation name is 'clk_scan', type is output
clk_scan = _LC6_C14;
-- Node name is ':141' = 'i0'
-- Equation name is 'i0', location is LC8_E2, type is buried.
!i0 = i0~NOT;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?