tiaoping.tan.qmsg

条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能

{ "Info" "ITDB_TH_RESULT" "temp\[7\] din\[7\] wr 0.900 ns register " "Info: th for register \"temp\[7\]\" (data pin = \"din\[7\]\", clock pin = \"wr\") is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 6.500 ns + Longest register " "Info: + Longest clock path from clock \"wr\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns wr 1 CLK PIN_10 47 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_10; Fanout = 47; CLK Node = 'wr'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { wr } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.500 ns) 6.500 ns temp\[7\] 2 REG LC32 2 " "Info: 2: + IC(2.600 ns) + CELL(2.500 ns) = 6.500 ns; Loc. = LC32; Fanout = 2; REG Node = 'temp\[7\]'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "5.100 ns" { wr temp[7] } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 60.00 % " "Info: Total cell delay = 3.900 ns ( 60.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 40.00 % " "Info: Total interconnect delay = 2.600 ns ( 40.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "6.500 ns" { wr temp[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { wr wr~out temp[7] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 2.500ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns din\[7\] 1 PIN PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_23; Fanout = 1; PIN Node = 'din\[7\]'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { din[7] } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 6.900 ns temp\[7\] 2 REG LC32 2 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC32; Fanout = 2; REG Node = 'temp\[7\]'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "5.500 ns" { din[7] temp[7] } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 66.67 % " "Info: Total cell delay = 4.600 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 33.33 % " "Info: Total interconnect delay = 2.300 ns ( 33.33 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "6.900 ns" { din[7] temp[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.900 ns" { din[7] din[7]~out temp[7] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } } }  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "6.500 ns" { wr temp[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { wr wr~out temp[7] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 2.500ns } } } { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "6.900 ns" { din[7] temp[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.900 ns" { din[7] din[7]~out temp[7] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 13:33:41 2006 " "Info: Processing ended: Wed Mar 15 13:33:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}