tiaoping.tan.qmsg

来自「条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "p1_3 " "Info: Assuming node \"p1_3\" is an undefined clock" {  } { { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "p1_3" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wr " "Info: Assuming node \"wr\" is an undefined clock" {  } { { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 9 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "wr" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}