tiaoping.tan.qmsg

条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能

{ "Info" "ITDB_TSU_RESULT" "flag_low wr clk 7.400 ns register " "Info: tsu for register \"flag_low\" (data pin = \"wr\", clock pin = \"clk\") is 7.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.100 ns + Longest pin register " "Info: + Longest pin to register delay is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns wr 1 CLK PIN_10 47 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_10; Fanout = 47; CLK Node = 'wr'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { wr } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.200 ns) 5.200 ns flag_low~179 2 COMB LC56 1 " "Info: 2: + IC(2.600 ns) + CELL(1.200 ns) = 5.200 ns; Loc. = LC56; Fanout = 1; COMB Node = 'flag_low~179'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "3.800 ns" { wr flag_low~179 } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 8.100 ns flag_low 3 REG LC57 39 " "Info: 3: + IC(0.000 ns) + CELL(2.900 ns) = 8.100 ns; Loc. = LC57; Fanout = 39; REG Node = 'flag_low'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "2.900 ns" { flag_low~179 flag_low } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 67.90 % " "Info: Total cell delay = 5.500 ns ( 67.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 32.10 % " "Info: Total interconnect delay = 2.600 ns ( 32.10 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "8.100 ns" { wr flag_low~179 flag_low } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.100 ns" { wr wr~out flag_low~179 flag_low } { 0.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 1.400ns 1.200ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 13 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 13; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { clk } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns flag_low 2 REG LC57 39 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC57; Fanout = 39; REG Node = 'flag_low'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "1.300 ns" { clk flag_low } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "3.600 ns" { clk flag_low } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out flag_low } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "8.100 ns" { wr flag_low~179 flag_low } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.100 ns" { wr wr~out flag_low~179 flag_low } { 0.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 1.400ns 1.200ns 2.900ns } } } { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "3.600 ns" { clk flag_low } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out flag_low } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out clk_out~reg0 13.800 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 13.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 13 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 13; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { clk } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns clk_out~reg0 2 REG LC26 8 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC26; Fanout = 8; REG Node = 'clk_out~reg0'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "1.300 ns" { clk clk_out~reg0 } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "3.600 ns" { clk clk_out~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out clk_out~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LC26 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 8; REG Node = 'clk_out~reg0'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { clk_out~reg0 } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(4.500 ns) 6.800 ns clk_out~90 2 COMB LC17 1 " "Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 6.800 ns; Loc. = LC17; Fanout = 1; COMB Node = 'clk_out~90'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "6.800 ns" { clk_out~reg0 clk_out~90 } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 8.600 ns clk_out 3 PIN PIN_15 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.600 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'clk_out'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "1.800 ns" { clk_out~90 clk_out } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 73.26 % " "Info: Total cell delay = 6.300 ns ( 73.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 26.74 % " "Info: Total interconnect delay = 2.300 ns ( 26.74 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "8.600 ns" { clk_out~reg0 clk_out~90 clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk_out~reg0 clk_out~90 clk_out } { 0.000ns 2.300ns 0.000ns } { 0.000ns 4.500ns 1.800ns } } }  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "3.600 ns" { clk clk_out~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out clk_out~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "8.600 ns" { clk_out~reg0 clk_out~90 clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk_out~reg0 clk_out~90 clk_out } { 0.000ns 2.300ns 0.000ns } { 0.000ns 4.500ns 1.800ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "cpld_sel sel_out3 10.300 ns Longest " "Info: Longest tpd from source pin \"cpld_sel\" to destination pin \"sel_out3\" is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns cpld_sel 1 PIN PIN_42 59 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_42; Fanout = 59; PIN Node = 'cpld_sel'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "" { cpld_sel } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.500 ns) 8.500 ns sel_out3~13 2 COMB LC1 1 " "Info: 2: + IC(2.600 ns) + CELL(4.500 ns) = 8.500 ns; Loc. = LC1; Fanout = 1; COMB Node = 'sel_out3~13'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "7.100 ns" { cpld_sel sel_out3~13 } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 10.300 ns sel_out3 3 PIN PIN_6 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.300 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'sel_out3'" {  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "1.800 ns" { sel_out3~13 sel_out3 } "NODE_NAME" } "" } } { "tiaoping.vhd" "" { Text "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/tiaoping.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns 74.76 % " "Info: Total cell delay = 7.700 ns ( 74.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 25.24 % " "Info: Total interconnect delay = 2.600 ns ( 25.24 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" "" { Report "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping_cmp.qrpt" Compiler "tiaoping" "UNKNOWN" "V1" "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/db/tiaoping.quartus_db" { Floorplan "C:/Documents and Settings/zhenlin/桌面/条屏调试/cpld/" "" "10.300 ns" { cpld_sel sel_out3~13 sel_out3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.300 ns" { cpld_sel cpld_sel~out sel_out3~13 sel_out3 } { 0.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 1.400ns 4.500ns 1.800ns } } }  } 0}