t_add_rca_16.v.bak

Systemverilog 编写的贩卖机代码

module t_Add_rca_16();
	wire[15:0]		sum;
	reg[15:0]		a,b;
	wire				c_in;
	wire				c_out;
	
Add_rca_16_0_delay M1(.sum(sum),
												.c_out(c_out),
												.a(a),
												.b(b),
												.c_in(c_in));

	
	initial begin
		#10 a=0000000000000000;b=0000000000000000;
		#10 a=1111111111111111;b=0000000000000000;
		#10 a=1010101010101010;
	end
endmodule