add_full.v

来自「Systemverilog 编写的贩卖机代码」· Verilog 代码 · 共 8 行

module Add_full_0_delay(sum,c_out,a,b,c_in);
	output					c_out,sum;
	input						a,b,c_in;
	wire						w1,w2,w3;
	Add_half_0_delay M1 		(w1,w2,a,b);
	Add_half_0_delay M2 		(sum,w3,w2,c_in);
	or M3				(c_out,w2,w3);
endmodule