i2c_ack1.vhd

这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_ack1 is
port(
     fcore,reset: in std_logic;
     sda,ack_en:in std_logic;
     ack_i,extpp:buffer std_logic;
   --  ack_i1,ack_i2,ack_i3,ack_i4:buffer std_logic;
     scl,exnt_ack:out std_logic
    );
end i2c_ack1;
architecture behav of i2c_ack1 is
type t_states is(a,b,c,d);
signal t_state_c:t_states;
signal count:std_logic_vector(7 downto 0);
signal  ack_i2,ack_i1,ack_i3,ack_i4:std_logic;
begin
process(reset,fcore)
begin
if(extpp='1') then
 if(ack_i='1') then
  exnt_ack<='0';
 else
  exnt_ack<='1';
 end if;
 else
  exnt_ack<='0';
 end if;
if(reset='1') then
 count<=(others=>'0');
elsif rising_edge(fcore) then
 if(ack_en='1') then

  t_state_c<=a;
 count<=count+1;
 case t_state_c is
  when a=>
   scl<='0';
   if(count="00011101") then
    if(sda='1') then
     ack_i1<='1';
   -- else
     --ack_i1<='0';
    end if;
    t_state_c<=b;
   else
    t_state_c<=a;
       end if;
  when b=>
   scl<='1';
   if(count="00110001") then
    if(sda='1') then
     ack_i2<='1';
    --else 
   --  ack_i2<='0';
    end if;
    t_state_c<=c;
   else
    t_state_c<=b;
   end if;
  when c=>
   scl<='1';
   if(count="01000101") then
    if(sda='1') then
     ack_i3<='1';
   -- else 
   --  ack_i3<='0';
    end if;
    t_state_c<=d;
   else
    t_state_c<=c;
   end if;
  when d=>
   scl<='0';
  if(count="01100001") then
    
        if(sda='1') then
     ack_i4<='1';
    --else 
    -- ack_i4<='0';
    end if;
  end if;
  if(count="01100010") then
   extpp<='1';
  end if;
  if(count="01100011") then
    count<=(others=>'0');
  else
    t_state_c<=d;
   end if;

  end case;
ack_i<=ack_i1 and ack_i2 and ack_i3 and ack_i4;--connected with component i2c_top; 
 else
 ack_i<='0';
 ack_i1<='0';
ack_i2<='0';
ack_i3<='0';
ack_i4<='0';
  scl<='0';
  extpp<='0';
  --extpp<='0';
  --extpp1<='0';
 end if;
end if;
end process;
end behav;