i2csyn.vhd

来自「这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2csyn is
port(
     clk,reset:in std_logic;
     scl:out std_logic;
     ack_i,exnt_ack:buffer std_logic;
    fi2c,fcore:buffer std_logic;
     sda:inout std_logic
    );
end i2csyn;
architecture behav of i2csyn is
component i2c_cmd
port(clk,reset,ack_i:      in std_logic;
     --datain:         in std_logic_vector(7 downto 0);
     --addr:           in std_logic_vector(1 downto 0);
     fi2c,fcore:       out std_logic;
     start_i,stop_i:     out std_logic;
     txreg:  out std_logic_vector(7 downto 0);
     exnt_ack:   in std_logic
     --exnt:buffer std_logic
    );

end component;
component top_start
port(
     reset,fcore,fi2c,start_i,stop_i:in std_logic;
     tx:in std_logic_vector(7 downto 0);
     exnt_ack:out std_logic;
     scl:out std_logic;
     ack_i: buffer std_logic;
     sda:inout std_logic
     );
end component;
signal start_i,stop_i:std_logic;
signal tx:std_logic_vector(7 downto 0);
begin
t1:i2c_cmd port map(clk,reset,ack_i,fi2c,fcore,start_i,stop_i,tx,exnt_ack);
t2:top_start port map(reset,fcore,fi2c,start_i,stop_i,tx,exnt_ack,scl,ack_i,sda);
end behav;