i2c_stop.vhd

这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_stop is
port(
     fcore,reset:in std_logic; 
     stop_en:in std_logic;
     stp_i,scl:out std_logic;
    sda:inout std_logic
    );
end i2c_stop;
architecture behav of i2c_stop is
type t_states is(a,b,c,d);
signal t_state_d:t_states;
signal count:std_logic_vector(7 downto 0);
begin
process(fcore,reset)
begin
if(reset='1') then
count<=(others=>'0');
elsif rising_edge(fcore) then
if(stop_en='1') then
 t_state_d<=a;
count<=count+1;
 case t_state_d is
 when a=>
  scl<='0';
  sda<='0';
  if(count="00011000") then
   t_state_d<=b;
  else
   t_state_d<=a;
  end if;
 when b=>
  scl<='1';
  sda<='0';
  if(count="01000010") then
   t_state_d<=c;
  else 
   t_state_d<=b;
  end if;
 when c=>
  scl<='1';
  sda<='1';
  if(count="01001010") then
   t_state_d<=d;
  else
   t_state_d<=c;
  end if;
 when d=>
  scl<='0';
  sda<='1';
  if(count="01100010") then
   stp_i<='1';
  end if;
  if(count="01100011") then
   count<=(others=>'0');
  else
   t_state_d<=d;
  end if;
 end case;
 else
  stp_i<='0';
  scl<='0';
  sda<='0';
 end if;
 end if;
 end process;
end behav;