📄 i2c_tshift.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_tshift is
port(
fi2c:in std_logic;
tx:in std_logic_vector(7 downto 0);
shift_en1,shift_i,shift_temp:in std_logic;
shift_i1,shift_en,sda:out std_logic
);
end i2c_tshift;
architecture behav of i2c_tshift is
signal int:std_logic_vector(3 downto 0);
signal txtag,shift_again:std_logic;
signal txreg:std_logic_vector(7 downto 0);
begin
shift_again<=shift_en1 xor shift_temp;
b:process(fi2c)
begin
if(shift_again='1') then
txreg<=tx;
elsif rising_edge(fi2c) then
if(shift_en1='1' ) then
txreg<=txreg(6 downto 0)&txtag;
txtag<='0';
if(int="1000") then
shift_en<='0';
shift_i1<='1';
sda<='0';
else
sda<=txreg(7);
shift_en<='1';
end if;
else
shift_i1<='0';
end if;
end if;
end process b;
a:process(shift_i,shift_again)
begin
if(shift_again='1') then
int<="0000";
elsif rising_edge(shift_i) then
int<=int+1;
if(int="1000") then
int<="0000";
end if;
end if;
end process a;
end behav;
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