i2c_start.vhd

这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_start is
port(
     fcore,reset:in std_logic;
     strb: in std_logic;
     sda,wr,scl:out std_logic
    -- sda:inout std_logic
    );
end i2c_start;
architecture behav of i2c_start is
type t_states is(a,b,c,d);
signal t_state_a:t_states;
signal count:std_logic_vector(7 downto 0);
begin
process(reset,fcore)
begin
if(reset='1') then
count<=(others=>'0');
elsif rising_edge(fcore) then
if(strb='1') then
 t_state_a<=a;
 count<=count+1;
 case t_state_a is
  when a=>
   scl<='0';
   sda<='1';
   if(count="00011000") then
    t_state_a<=b;
   else
    t_state_a<=a;
   end if;
  when b=>
   scl<='1';
   sda<='1';
   if(count="00100000") then
    t_state_a<=c;
   else
    t_state_a<=b;
   end if;
  when c=>
   scl<='1';
   sda<='0';
   
   if(count="01001010") then
    t_state_a<=d;
       else
    t_state_a<=c;
   end if;
  when d=>
   scl<='0';
   sda<='0';
  if(count="01100010") then
   wr<='1';
  end if;
   if(count="01100011") then
   -- wr<='1';
    count<=(others=>'0');
   else
    t_state_a<=d;
   end if;
  end case;
 else
 wr<='0';
sda<='0';
scl<='0';
 end if;
end if;
end process;
end behav;