i2c_top.vhd

这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_top is
port(reset,fcore:      in std_logic;
     start_i,stop_i:  in std_logic;
     wr,shift_i1,ack_i,extpp,stp_i: in std_logic;
     strb,shift_temp,stop_en,ack_en: out std_logic;
     shift_en1:buffer std_logic;
     scl:            out std_logic;
     sda:            out std_logic
    );
end i2c_top;
architecture behav of i2c_top is
type states is(idle,start,shift,ack,stop);
signal state:states;
begin
cc: process(reset,fcore,start_i,stop_i)
begin
if(reset='1') then
 state<=idle;
elsif rising_edge(fcore) then
case state is
when idle=>
scl<='1';
sda<='1';
if(start_i='1') then
state<=start;
else
state<=idle;
end if;

when start=>
strb<='1';
if(wr='1') then--when start  end strobe the wr;
strb<='0';
state<=shift;
else 
state<=start;
end if;

when shift=>
shift_en1<='1';
 if(shift_en1='1') then
  shift_temp<='1';
 end if;
if(shift_i1='1') then
 state<=ack;
 shift_en1<='0';
 shift_temp<='0';
else
 state<=shift;
end if;

when ack=>
ack_en<='1';
if(extpp='1') then
ack_en<='0';
if(ack_i='1') then
  state<=shift;
elsif(stop_i='1') then
    state<=stop;
end if;
end if;

when stop=>
stop_en<='1';
if(stp_i='1') then
stop_en<='0';
state<=idle;
else
state<=stop;
end if;
end case;
end if;
end process cc;
end behav;