📄 i2c_shift.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c_shift is
port(
fcore,reset:in std_logic;
shift_en:in std_logic;
scl,shift_i:out std_logic
);
end i2c_shift;
architecture behav of i2c_shift is
type t_states is (a,b,c,d);
signal t_state_b: t_states;
signal counta:std_logic_vector(7 downto 0);
begin
process(reset,fcore)
begin
if(reset='1') then
counta<=(others=>'0');
elsif rising_edge(fcore) then
if(shift_en='1') then
t_state_b<=a;
counta<=counta+1;
case t_state_b is
when a=>
scl<='0';
shift_i<='0';
if(counta="00011101") then
t_state_b<=b;
else
t_state_b<=a;
end if;
when b=>
scl<='1';
if(counta="00110001") then
t_state_b<=c;
else
t_state_b<=b;
end if;
when c=>
scl<='1';
if(counta="01000101") then
t_state_b<=d;
else
t_state_b<=c;
end if;
when d=>
scl<='0';
if(counta="01100010") then
shift_i<='1';
end if;
if(counta="01100011") then
counta<=(others=>'0');
else
t_state_b<=d;
end if;
end case;
else
scl<='0';
shift_i<='0';
end if;
end if;
end process;
end behav;
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