decoder.v

采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理

//=============decoder.v=============//
module decoder(s1,s2,s3,s4,s5,s6,s7,s8,a,b,c,d,e,f,g);
     input s1,s2,s3,s4,s5,s6,s7,s8;
     output a,b,c,d,e,f,g;
     reg a,b,c,d,e,f,g;
     
     reg[8:1] tempin;
     reg[7:1] tempout;
     
     always @(s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8)
       begin
         assign tempin={s1,s2,s3,s4,s5,s6,s7,s8};
         case(tempin)
           8'b10000000 :tempout<=7'b0110000;
           8'b01000000 :tempout<=7'b1101101;
           8'b00100000 :tempout<=7'b1111001;
           8'b00010000 :tempout<=7'b0110011;
           8'b00001000 :tempout<=7'b1011011;
           8'b00000100 :tempout<=7'b1011111;
           8'b00000010 :tempout<=7'b1110000;
           8'b00000001 :tempout<=7'b1111111;
           8'b00000000 :tempout<=7'b0000000;
           default	   :tempout<=7'b0000000;
         endcase
         assign {a,b,c,d,e,f,g}=tempout[7:1];
      end
endmodule