📄 clkdiv.rpt
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-- Node name is ':184' = 'clk_count20'
-- Equation name is 'clk_count20', location is LC3_B13, type is buried.
clk_count20 = DFFE( _EQ021, GLOBAL( clkin), VCC, VCC, VCC);
_EQ021 = !clk_count19 & clk_count20 & _LC6_B13
# clk_count20 & !_LC5_B15 & _LC6_B13
# clk_count19 & !clk_count20 & _LC5_B15 & _LC6_B13;
-- Node name is ':183' = 'clk_count21'
-- Equation name is 'clk_count21', location is LC7_B13, type is buried.
clk_count21 = DFFE( _EQ022, GLOBAL( clkin), VCC, VCC, VCC);
_EQ022 = clk_count21 & !_LC5_B13 & _LC6_B13
# !clk_count21 & _LC5_B13 & _LC6_B13;
-- Node name is ':182' = 'clk_count22'
-- Equation name is 'clk_count22', location is LC4_B13, type is buried.
clk_count22 = DFFE( _EQ023, GLOBAL( clkin), VCC, VCC, VCC);
_EQ023 = clk_count22 & !_LC2_B13 & _LC6_B13
# !clk_count22 & _LC2_B13 & _LC6_B13;
-- Node name is ':181' = 'clk_count23'
-- Equation name is 'clk_count23', location is LC8_B13, type is buried.
clk_count23 = DFFE( _EQ024, GLOBAL( clkin), VCC, VCC, VCC);
_EQ024 = !clk_count22 & clk_count23 & _LC6_B13
# clk_count23 & !_LC2_B13 & _LC6_B13
# clk_count22 & !clk_count23 & _LC2_B13 & _LC6_B13;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = _LC1_B13;
-- Node name is '|lpm_add_sub:209|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B16', type is buried
!_LC2_B16 = _LC2_B16~NOT;
_LC2_B16~NOT = LCELL( _EQ025);
_EQ025 = !clk_count0
# !clk_count1;
-- Node name is '|lpm_add_sub:209|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B16', type is buried
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ026);
_EQ026 = !clk_count3
# !clk_count2
# !_LC2_B16;
-- Node name is '|lpm_add_sub:209|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B16', type is buried
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL( _EQ027);
_EQ027 = !clk_count4
# !_LC3_B16;
-- Node name is '|lpm_add_sub:209|addcore:adder|:159' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ028);
_EQ028 = clk_count5 & clk_count6 & clk_count7 & _LC1_B16;
-- Node name is '|lpm_add_sub:209|addcore:adder|:163' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = LCELL( _EQ029);
_EQ029 = clk_count8 & _LC4_B23;
-- Node name is '|lpm_add_sub:209|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = LCELL( _EQ030);
_EQ030 = clk_count8 & clk_count9 & clk_count10 & _LC4_B23;
-- Node name is '|lpm_add_sub:209|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ031);
_EQ031 = clk_count11 & clk_count12 & _LC5_B17;
-- Node name is '|lpm_add_sub:209|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B17', type is buried
_LC8_B17 = LCELL( _EQ032);
_EQ032 = clk_count11 & clk_count12 & clk_count13 & _LC5_B17;
-- Node name is '|lpm_add_sub:209|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B15', type is buried
_LC3_B15 = LCELL( _EQ033);
_EQ033 = clk_count14 & clk_count15 & _LC8_B17;
-- Node name is '|lpm_add_sub:209|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B15', type is buried
_LC7_B15 = LCELL( _EQ034);
_EQ034 = clk_count14 & clk_count15 & clk_count16 & _LC8_B17;
-- Node name is '|lpm_add_sub:209|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B15', type is buried
_LC5_B15 = LCELL( _EQ035);
_EQ035 = clk_count17 & clk_count18 & _LC7_B15;
-- Node name is '|lpm_add_sub:209|addcore:adder|:211' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ036);
_EQ036 = clk_count19 & clk_count20 & _LC5_B15;
-- Node name is '|lpm_add_sub:209|addcore:adder|:215' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ037);
_EQ037 = clk_count19 & clk_count20 & clk_count21 & _LC5_B15;
-- Node name is ':12'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ038);
_EQ038 = !clk_count23
# !clk_count21 & !clk_count22 & _LC2_B18;
-- Node name is ':27'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ039);
_EQ039 = !clk_count18 & _LC4_B15
# !clk_count19
# !clk_count20;
-- Node name is '~34~1'
-- Equation name is '~34~1', location is LC4_B15, type is buried.
-- synthesized logic cell
_LC4_B15 = LCELL( _EQ040);
_EQ040 = !clk_count15 & !clk_count16 & !clk_count17
# !clk_count16 & !clk_count17 & _LC8_B18;
-- Node name is ':54'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ041);
_EQ041 = !clk_count12 & !clk_count13 & !clk_count14
# !clk_count13 & !clk_count14 & _LC4_B17;
-- Node name is ':69'
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = LCELL( _EQ042);
_EQ042 = !clk_count11 & _LC1_B23
# !clk_count9 & !clk_count11
# !clk_count10 & !clk_count11;
-- Node name is ':84'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ043);
_EQ043 = !clk_count7 & !clk_count8 & _LC3_B23;
-- Node name is ':97'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ044);
_EQ044 = !clk_count6
# !clk_count5
# !_LC1_B16;
-- Node name is ':208'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( _EQ045, GLOBAL( clkin), VCC, VCC, VCC);
_EQ045 = clk_count22 & clk_count23
# clk_count21 & clk_count23
# clk_count23 & !_LC2_B18;
Project Information f:\verilog hdl\clkscan\clkscan2\clkdiv.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,989K
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