📄 clkdiv.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 16 OR2 ! 0 2 0 3 |lpm_add_sub:209|addcore:adder|:135
- 3 - B 16 OR2 ! 0 3 0 2 |lpm_add_sub:209|addcore:adder|:143
- 1 - B 16 OR2 ! 0 2 0 4 |lpm_add_sub:209|addcore:adder|:147
- 4 - B 23 AND2 0 4 0 4 |lpm_add_sub:209|addcore:adder|:159
- 6 - B 23 AND2 0 2 0 1 |lpm_add_sub:209|addcore:adder|:163
- 5 - B 17 AND2 0 4 0 4 |lpm_add_sub:209|addcore:adder|:171
- 3 - B 17 AND2 0 3 0 1 |lpm_add_sub:209|addcore:adder|:179
- 8 - B 17 AND2 0 4 0 4 |lpm_add_sub:209|addcore:adder|:183
- 3 - B 15 AND2 0 3 0 1 |lpm_add_sub:209|addcore:adder|:191
- 7 - B 15 AND2 0 4 0 3 |lpm_add_sub:209|addcore:adder|:195
- 5 - B 15 AND2 0 3 0 4 |lpm_add_sub:209|addcore:adder|:203
- 5 - B 13 AND2 0 3 0 1 |lpm_add_sub:209|addcore:adder|:211
- 2 - B 13 AND2 0 4 0 2 |lpm_add_sub:209|addcore:adder|:215
- 6 - B 13 OR2 0 4 0 24 :12
- 2 - B 18 OR2 0 4 0 2 :27
- 4 - B 15 OR2 s 0 4 0 1 ~34~1
- 8 - B 18 OR2 0 4 0 1 :54
- 4 - B 17 OR2 0 4 0 1 :69
- 1 - B 23 AND2 0 3 0 1 :84
- 3 - B 23 OR2 0 3 0 2 :97
- 8 - B 13 DFFE + 0 3 0 2 clk_count23 (:181)
- 4 - B 13 DFFE + 0 2 0 3 clk_count22 (:182)
- 7 - B 13 DFFE + 0 2 0 3 clk_count21 (:183)
- 3 - B 13 DFFE + 0 3 0 3 clk_count20 (:184)
- 6 - B 18 DFFE + 0 2 0 4 clk_count19 (:185)
- 2 - B 15 DFFE + 0 3 0 2 clk_count18 (:186)
- 8 - B 15 DFFE + 0 2 0 3 clk_count17 (:187)
- 6 - B 15 DFFE + 0 2 0 2 clk_count16 (:188)
- 1 - B 15 DFFE + 0 3 0 3 clk_count15 (:189)
- 5 - B 18 DFFE + 0 2 0 4 clk_count14 (:190)
- 1 - B 18 DFFE + 0 2 0 2 clk_count13 (:191)
- 7 - B 17 DFFE + 0 3 0 3 clk_count12 (:192)
- 6 - B 17 DFFE + 0 2 0 4 clk_count11 (:193)
- 2 - B 17 DFFE + 0 3 0 2 clk_count10 (:194)
- 1 - B 17 DFFE + 0 3 0 3 clk_count9 (:195)
- 2 - B 23 DFFE + 0 2 0 4 clk_count8 (:196)
- 8 - B 23 DFFE + 0 2 0 2 clk_count7 (:197)
- 7 - B 23 DFFE + 0 3 0 2 clk_count6 (:198)
- 5 - B 23 DFFE + 0 2 0 3 clk_count5 (:199)
- 8 - B 16 DFFE + 0 2 0 1 clk_count4 (:200)
- 6 - B 16 DFFE + 0 3 0 1 clk_count3 (:201)
- 7 - B 16 DFFE + 0 2 0 2 clk_count2 (:202)
- 5 - B 16 DFFE + 0 2 0 1 clk_count1 (:203)
- 4 - B 16 DFFE + 0 1 0 2 clk_count0 (:204)
- 1 - B 13 DFFE + 0 4 1 0 :208
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\verilog hdl\clkscan\clkscan2\clkdiv.rpt
clkdiv
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 20/ 48( 41%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog hdl\clkscan\clkscan2\clkdiv.rpt
clkdiv
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 clkin
Device-Specific Information: f:\verilog hdl\clkscan\clkscan2\clkdiv.rpt
clkdiv
** EQUATIONS **
clkin : INPUT;
-- Node name is ':204' = 'clk_count0'
-- Equation name is 'clk_count0', location is LC4_B16, type is buried.
clk_count0 = DFFE( _EQ001, GLOBAL( clkin), VCC, VCC, VCC);
_EQ001 = !clk_count0 & _LC6_B13;
-- Node name is ':203' = 'clk_count1'
-- Equation name is 'clk_count1', location is LC5_B16, type is buried.
clk_count1 = DFFE( _EQ002, GLOBAL( clkin), VCC, VCC, VCC);
_EQ002 = clk_count0 & !clk_count1 & _LC6_B13
# !clk_count0 & clk_count1 & _LC6_B13;
-- Node name is ':202' = 'clk_count2'
-- Equation name is 'clk_count2', location is LC7_B16, type is buried.
clk_count2 = DFFE( _EQ003, GLOBAL( clkin), VCC, VCC, VCC);
_EQ003 = clk_count2 & !_LC2_B16 & _LC6_B13
# !clk_count2 & _LC2_B16 & _LC6_B13;
-- Node name is ':201' = 'clk_count3'
-- Equation name is 'clk_count3', location is LC6_B16, type is buried.
clk_count3 = DFFE( _EQ004, GLOBAL( clkin), VCC, VCC, VCC);
_EQ004 = !clk_count2 & clk_count3 & _LC6_B13
# clk_count3 & !_LC2_B16 & _LC6_B13
# clk_count2 & !clk_count3 & _LC2_B16 & _LC6_B13;
-- Node name is ':200' = 'clk_count4'
-- Equation name is 'clk_count4', location is LC8_B16, type is buried.
clk_count4 = DFFE( _EQ005, GLOBAL( clkin), VCC, VCC, VCC);
_EQ005 = clk_count4 & !_LC3_B16 & _LC6_B13
# !clk_count4 & _LC3_B16 & _LC6_B13;
-- Node name is ':199' = 'clk_count5'
-- Equation name is 'clk_count5', location is LC5_B23, type is buried.
clk_count5 = DFFE( _EQ006, GLOBAL( clkin), VCC, VCC, VCC);
_EQ006 = clk_count5 & !_LC1_B16 & _LC6_B13
# !clk_count5 & _LC1_B16 & _LC6_B13;
-- Node name is ':198' = 'clk_count6'
-- Equation name is 'clk_count6', location is LC7_B23, type is buried.
clk_count6 = DFFE( _EQ007, GLOBAL( clkin), VCC, VCC, VCC);
_EQ007 = !clk_count5 & clk_count6 & _LC6_B13
# clk_count6 & !_LC1_B16 & _LC6_B13
# clk_count5 & !clk_count6 & _LC1_B16 & _LC6_B13;
-- Node name is ':197' = 'clk_count7'
-- Equation name is 'clk_count7', location is LC8_B23, type is buried.
clk_count7 = DFFE( _EQ008, GLOBAL( clkin), VCC, VCC, VCC);
_EQ008 = clk_count7 & _LC3_B23 & _LC6_B13
# !clk_count7 & !_LC3_B23 & _LC6_B13;
-- Node name is ':196' = 'clk_count8'
-- Equation name is 'clk_count8', location is LC2_B23, type is buried.
clk_count8 = DFFE( _EQ009, GLOBAL( clkin), VCC, VCC, VCC);
_EQ009 = clk_count8 & !_LC4_B23 & _LC6_B13
# !clk_count8 & _LC4_B23 & _LC6_B13;
-- Node name is ':195' = 'clk_count9'
-- Equation name is 'clk_count9', location is LC1_B17, type is buried.
clk_count9 = DFFE( _EQ010, GLOBAL( clkin), VCC, VCC, VCC);
_EQ010 = !clk_count8 & clk_count9 & _LC6_B13
# clk_count9 & !_LC4_B23 & _LC6_B13
# clk_count8 & !clk_count9 & _LC4_B23 & _LC6_B13;
-- Node name is ':194' = 'clk_count10'
-- Equation name is 'clk_count10', location is LC2_B17, type is buried.
clk_count10 = DFFE( _EQ011, GLOBAL( clkin), VCC, VCC, VCC);
_EQ011 = !clk_count9 & clk_count10 & _LC6_B13
# clk_count10 & _LC6_B13 & !_LC6_B23
# clk_count9 & !clk_count10 & _LC6_B13 & _LC6_B23;
-- Node name is ':193' = 'clk_count11'
-- Equation name is 'clk_count11', location is LC6_B17, type is buried.
clk_count11 = DFFE( _EQ012, GLOBAL( clkin), VCC, VCC, VCC);
_EQ012 = clk_count11 & !_LC5_B17 & _LC6_B13
# !clk_count11 & _LC5_B17 & _LC6_B13;
-- Node name is ':192' = 'clk_count12'
-- Equation name is 'clk_count12', location is LC7_B17, type is buried.
clk_count12 = DFFE( _EQ013, GLOBAL( clkin), VCC, VCC, VCC);
_EQ013 = !clk_count11 & clk_count12 & _LC6_B13
# clk_count12 & !_LC5_B17 & _LC6_B13
# clk_count11 & !clk_count12 & _LC5_B17 & _LC6_B13;
-- Node name is ':191' = 'clk_count13'
-- Equation name is 'clk_count13', location is LC1_B18, type is buried.
clk_count13 = DFFE( _EQ014, GLOBAL( clkin), VCC, VCC, VCC);
_EQ014 = clk_count13 & !_LC3_B17 & _LC6_B13
# !clk_count13 & _LC3_B17 & _LC6_B13;
-- Node name is ':190' = 'clk_count14'
-- Equation name is 'clk_count14', location is LC5_B18, type is buried.
clk_count14 = DFFE( _EQ015, GLOBAL( clkin), VCC, VCC, VCC);
_EQ015 = clk_count14 & _LC6_B13 & !_LC8_B17
# !clk_count14 & _LC6_B13 & _LC8_B17;
-- Node name is ':189' = 'clk_count15'
-- Equation name is 'clk_count15', location is LC1_B15, type is buried.
clk_count15 = DFFE( _EQ016, GLOBAL( clkin), VCC, VCC, VCC);
_EQ016 = !clk_count14 & clk_count15 & _LC6_B13
# clk_count15 & _LC6_B13 & !_LC8_B17
# clk_count14 & !clk_count15 & _LC6_B13 & _LC8_B17;
-- Node name is ':188' = 'clk_count16'
-- Equation name is 'clk_count16', location is LC6_B15, type is buried.
clk_count16 = DFFE( _EQ017, GLOBAL( clkin), VCC, VCC, VCC);
_EQ017 = clk_count16 & !_LC3_B15 & _LC6_B13
# !clk_count16 & _LC3_B15 & _LC6_B13;
-- Node name is ':187' = 'clk_count17'
-- Equation name is 'clk_count17', location is LC8_B15, type is buried.
clk_count17 = DFFE( _EQ018, GLOBAL( clkin), VCC, VCC, VCC);
_EQ018 = clk_count17 & _LC6_B13 & !_LC7_B15
# !clk_count17 & _LC6_B13 & _LC7_B15;
-- Node name is ':186' = 'clk_count18'
-- Equation name is 'clk_count18', location is LC2_B15, type is buried.
clk_count18 = DFFE( _EQ019, GLOBAL( clkin), VCC, VCC, VCC);
_EQ019 = !clk_count17 & clk_count18 & _LC6_B13
# clk_count18 & _LC6_B13 & !_LC7_B15
# clk_count17 & !clk_count18 & _LC6_B13 & _LC7_B15;
-- Node name is ':185' = 'clk_count19'
-- Equation name is 'clk_count19', location is LC6_B18, type is buried.
clk_count19 = DFFE( _EQ020, GLOBAL( clkin), VCC, VCC, VCC);
_EQ020 = clk_count19 & !_LC5_B15 & _LC6_B13
# !clk_count19 & _LC5_B15 & _LC6_B13;
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