📄 clkscan2_old.rpt
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13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan2\clkscan2_old.rpt
clkscan2_old
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 clk
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan2\clkscan2_old.rpt
clkscan2_old
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 13 reset
INPUT 8 start
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan2\clkscan2_old.rpt
clkscan2_old
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is ':23' = 'count0'
-- Equation name is 'count0', location is LC4_A10, type is buried.
!count0 = count0~NOT;
count0~NOT = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!start), VCC, _LC6_A11);
_EQ001 = count0
# !_LC1_A10;
-- Node name is ':22' = 'count1'
-- Equation name is 'count1', location is LC3_A10, type is buried.
!count1 = count1~NOT;
count1~NOT = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!start), VCC, _LC6_A11);
_EQ002 = !_LC1_A10
# count0 & count1
# !count0 & !count1;
-- Node name is ':21' = 'count2'
-- Equation name is 'count2', location is LC5_A10, type is buried.
!count2 = count2~NOT;
count2~NOT = DFFE(!_LC8_A10, GLOBAL( clk), GLOBAL(!start), VCC, _LC6_A11);
-- Node name is ':20' = 'count3'
-- Equation name is 'count3', location is LC7_A10, type is buried.
!count3 = count3~NOT;
count3~NOT = DFFE(!_LC6_A10, GLOBAL( clk), GLOBAL(!start), VCC, _LC6_A11);
-- Node name is ':15' = 'run'
-- Equation name is 'run', location is LC7_A11, type is buried.
run = DFFE( VCC, GLOBAL( clk), GLOBAL(!reset), GLOBAL(!start), start);
-- Node name is 'scan_data0'
-- Equation name is 'scan_data0', type is output
scan_data0 = _LC5_A11;
-- Node name is 'scan_data1'
-- Equation name is 'scan_data1', type is output
scan_data1 = _LC2_A10;
-- Node name is 'scan_data2'
-- Equation name is 'scan_data2', type is output
scan_data2 = _LC1_A11;
-- Node name is 'scan_data3'
-- Equation name is 'scan_data3', type is output
scan_data3 = _LC8_A11;
-- Node name is 'scan_en0'
-- Equation name is 'scan_en0', type is output
scan_en0 = _LC5_A1;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC1_A1;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC2_A1;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC3_A1;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC4_A1;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC7_A1;
-- Node name is 'start~1'
-- Equation name is 'start~1', location is LC1_A8, type is buried.
-- synthesized logic cell
!_LC1_A8 = _LC1_A8~NOT;
_LC1_A8~NOT = LCELL(!start);
-- Node name is ':119' = 'state0'
-- Equation name is 'state0', location is LC8_A8, type is buried.
state0 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, !_LC2_A8);
_EQ003 = _LC2_A11 & !state0;
-- Node name is ':118' = 'state1'
-- Equation name is 'state1', location is LC4_A11, type is buried.
state1 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, !_LC2_A8);
_EQ004 = _LC2_A11 & state0 & !state1
# _LC2_A11 & !state0 & state1;
-- Node name is ':117' = 'state2'
-- Equation name is 'state2', location is LC6_A1, type is buried.
state2 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, !_LC2_A8);
_EQ005 = _LC2_A11 & !_LC8_A1 & state2
# _LC2_A11 & _LC8_A1 & !state2;
-- Node name is '|lpm_add_sub:193|addcore:adder|:51' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ006);
_EQ006 = state0 & state1;
-- Node name is ':18'
-- Equation name is '_LC6_A11', type is buried
_LC6_A11 = LCELL( _EQ007);
_EQ007 = !reset & run;
-- Node name is ':41'
-- Equation name is '_LC1_A10', type is buried
!_LC1_A10 = _LC1_A10~NOT;
_LC1_A10~NOT = LCELL( _EQ008);
_EQ008 = count0 & count3
# count2 & count3
# count1 & count3;
-- Node name is ':58'
-- Equation name is '_LC6_A10', type is buried
!_LC6_A10 = _LC6_A10~NOT;
_LC6_A10~NOT = LCELL( _EQ009);
_EQ009 = count0 & count3
# count2 & count3
# count1 & count3
# !count0 & !count3
# !count1 & !count3
# !count2 & !count3;
-- Node name is ':59'
-- Equation name is '_LC8_A10', type is buried
!_LC8_A10 = _LC8_A10~NOT;
_LC8_A10~NOT = LCELL( _EQ010);
_EQ010 = count0 & count1 & count2
# !count0 & !count2
# !count1 & !count2
# !_LC1_A10;
-- Node name is ':72'
-- Equation name is '_LC8_A11', type is buried
_LC8_A11 = DFFE( _LC6_A10, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC3_A11);
-- Node name is ':73'
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = DFFE( _LC8_A10, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC3_A11);
-- Node name is ':74'
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = DFFE( _EQ011, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC3_A11);
_EQ011 = count0 & !count1 & _LC1_A10
# !count0 & count1 & _LC1_A10;
-- Node name is ':75'
-- Equation name is '_LC5_A11', type is buried
_LC5_A11 = DFFE( _EQ012, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC3_A11);
_EQ012 = !count0 & _LC1_A10;
-- Node name is ':77'
-- Equation name is '_LC3_A11', type is buried
!_LC3_A11 = _LC3_A11~NOT;
_LC3_A11~NOT = LCELL( _EQ013);
_EQ013 = run & !start;
-- Node name is '~107~1'
-- Equation name is '~107~1', location is LC2_A11, type is buried.
-- synthesized logic cell
_LC2_A11 = LCELL( _EQ014);
_EQ014 = _LC6_A11 & !state2
# _LC6_A11 & !state0 & !state1;
-- Node name is ':121'
-- Equation name is '_LC2_A8', type is buried
!_LC2_A8 = _LC2_A8~NOT;
_LC2_A8~NOT = LCELL( _EQ015);
_EQ015 = !reset & !start;
-- Node name is ':180'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = DFFE( _EQ016, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC1_A8);
_EQ016 = state0 & !state1 & state2;
-- Node name is ':181'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( _EQ017, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC1_A8);
_EQ017 = !state0 & !state1 & state2;
-- Node name is ':182'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ018, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC1_A8);
_EQ018 = state0 & state1 & !state2;
-- Node name is ':183'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _EQ019, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC1_A8);
_EQ019 = !state0 & state1 & !state2;
-- Node name is ':184'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ020, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC1_A8);
_EQ020 = state0 & !state1 & !state2;
-- Node name is ':185'
-- Equation name is '_LC5_A1', type is buried
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = DFFE( _EQ021, GLOBAL( clk), GLOBAL(!reset), VCC, !_LC1_A8);
_EQ021 = state0
# state1
# state2;
Project Informatione:\amj\eda\2003\experiment\clkscan\clkscan2\clkscan2_old.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:03
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:10
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,199K
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