📄 clkscan2.rpt
字号:
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2.rpt
clkscan2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
INPUT 1 start
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2.rpt
clkscan2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 12 reset
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2.rpt
clkscan2
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is ':52' = 'enable'
-- Equation name is 'enable', location is LC1_C8, type is buried.
enable = DFFE( VCC, GLOBAL( start), GLOBAL(!reset), VCC, VCC);
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC4_C8, type is buried.
-- synthesized logic cell
!_LC4_C8 = _LC4_C8~NOT;
_LC4_C8~NOT = LCELL(!reset);
-- Node name is 'scan_data0'
-- Equation name is 'scan_data0', type is output
scan_data0 = _LC8_C18;
-- Node name is 'scan_data1'
-- Equation name is 'scan_data1', type is output
scan_data1 = _LC7_C18;
-- Node name is 'scan_data2'
-- Equation name is 'scan_data2', type is output
scan_data2 = _LC1_C18;
-- Node name is 'scan_data3'
-- Equation name is 'scan_data3', type is output
scan_data3 = _LC3_C18;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC3_C6;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC6_C6;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC2_C8;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC5_C8;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC7_C8;
-- Node name is 'scan_en6'
-- Equation name is 'scan_en6', type is output
scan_en6 = _LC1_C6;
-- Node name is ':74' = 'state0'
-- Equation name is 'state0', location is LC6_C8, type is buried.
state0 = DFFE( _EQ001, GLOBAL(!clk), VCC, VCC, !_LC4_C8);
_EQ001 = !enable
# !state0
# !_LC3_C8;
-- Node name is ':73' = 'state1'
-- Equation name is 'state1', location is LC5_C6, type is buried.
state1 = DFFE( _EQ002, GLOBAL(!clk), VCC, VCC, !_LC4_C8);
_EQ002 = enable & _LC4_C6;
-- Node name is ':72' = 'state2'
-- Equation name is 'state2', location is LC2_C6, type is buried.
state2 = DFFE( _EQ003, GLOBAL(!clk), VCC, VCC, !_LC4_C8);
_EQ003 = enable & _LC3_C8 & _LC7_C6;
-- Node name is '|lpm_add_sub:168|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C18', type is buried
_LC4_C18 = LCELL( _EQ004);
_EQ004 = _LC7_C18 & _LC8_C18;
-- Node name is '|lpm_add_sub:168|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C18', type is buried
_LC5_C18 = LCELL( _EQ005);
_EQ005 = _LC1_C18 & _LC7_C18 & _LC8_C18;
-- Node name is '|lpm_add_sub:169|addcore:adder|:60' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C6', type is buried
_LC7_C6 = LCELL( _EQ006);
_EQ006 = !state0 & state2
# !state1 & state2
# state0 & state1 & !state2;
-- Node name is ':24'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = LCELL( _EQ007);
_EQ007 = !_LC3_C18
# !_LC1_C18 & !_LC7_C18 & !_LC8_C18;
-- Node name is ':54'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = DFFE( _EQ008, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ008 = _LC2_C18 & _LC3_C18 & !_LC5_C18
# _LC2_C18 & !_LC3_C18 & _LC5_C18;
-- Node name is ':55'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = DFFE( _EQ009, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ009 = _LC1_C18 & _LC2_C18 & !_LC4_C18
# !_LC1_C18 & _LC2_C18 & _LC4_C18;
-- Node name is ':56'
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = DFFE( _EQ010, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ010 = _LC2_C18 & _LC7_C18 & !_LC8_C18
# _LC2_C18 & !_LC7_C18 & _LC8_C18;
-- Node name is ':57'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = DFFE( _EQ011, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ011 = _LC2_C18 & !_LC8_C18;
-- Node name is ':78'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ012);
_EQ012 = !state2
# !state1;
-- Node name is ':96'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = LCELL( _EQ013);
_EQ013 = _LC3_C8 & state0 & !state1
# _LC3_C8 & !state0 & state1;
-- Node name is ':101'
-- Equation name is '_LC8_C6', type is buried
!_LC8_C6 = _LC8_C6~NOT;
_LC8_C6~NOT = LCELL( _EQ014);
_EQ014 = _LC3_C8 & _LC7_C6
# _LC3_C8 & state0
# _LC4_C6;
-- Node name is ':156'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = DFFE( _EQ015, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ015 = _LC4_C6 & _LC7_C6 & state0;
-- Node name is ':157'
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = DFFE( _EQ016, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ016 = !state0 & !state1 & state2;
-- Node name is ':158'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = DFFE( _EQ017, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ017 = state0 & state1 & !state2;
-- Node name is ':159'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = DFFE( _EQ018, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ018 = !state0 & state1 & !state2;
-- Node name is ':160'
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = DFFE( _EQ019, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
_EQ019 = _LC4_C6 & !_LC7_C6 & state0;
-- Node name is ':161'
-- Equation name is '_LC3_C6', type is buried
!_LC3_C6 = _LC3_C6~NOT;
_LC3_C6~NOT = DFFE(!_LC8_C6, GLOBAL(!clk), GLOBAL(!reset), VCC, enable);
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,083K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -