clkscan2.v.bak

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

//实验内容2
module clkscan2(clk,reset,start,scan_data,scan_en);
  input clk,reset,start;
  output[3:0] scan_data;
  output[5:0] scan_en;
  reg[5:0] scan_en;
  reg[3:0] scan_data,count;
  reg run;
  reg[2:0] state;
 `define s0 3'b000
 `define s1 3'b001
 `define s2 3'b010
 `define s3 3'b011
 `define s4 3'b100
 `define s5 3'b101

//产生一些控制  
  always @(posedge clk)
    begin
      if(reset) begin scan_data[3:0]=0;run=0;scan_en=1;end
     // else 
        if(start) begin count[3:0]=-1;run=1;end
   			scan_en[0]=(state==`s0);//产生七段码的使能
    		scan_en[1]=(state==`s1);
   	        scan_en[2]=(state==`s2);
    	    scan_en[3]=(state==`s3);
     		scan_en[4]=(state==`s4);
    		scan_en[5]=(state==`s5);

            if(run && !reset)
              begin                //循环数据0－9
				if(count[3:0]<9) count[3:0]=count[3:0]+1;
                else count[3:0]=0;
                scan_data=count;  
				if(state>=`s5) state=`s0;//使能端的状态
	  		    else state=state+3'b001;
			  end
            else  state = {1'bz,2'bz};

          
    end
    
endmodule