📄 clkscan1.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1.rpt
clkscan1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 2/ 96( 2%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1.rpt
clkscan1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk
INPUT 1 start
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1.rpt
clkscan1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1.rpt
clkscan1
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is ':51' = 'enable'
-- Equation name is 'enable', location is LC3_B11, type is buried.
enable = DFFE( VCC, GLOBAL( start), GLOBAL(!reset), VCC, VCC);
-- Node name is 'scan_data0'
-- Equation name is 'scan_data0', type is output
scan_data0 = _LC2_B11;
-- Node name is 'scan_data1'
-- Equation name is 'scan_data1', type is output
scan_data1 = _LC1_B11;
-- Node name is 'scan_data2'
-- Equation name is 'scan_data2', type is output
scan_data2 = _LC6_B11;
-- Node name is 'scan_data3'
-- Equation name is 'scan_data3', type is output
scan_data3 = _LC4_B11;
-- Node name is 'scan_en0'
-- Equation name is 'scan_en0', type is output
scan_en0 = _LC3_C3;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC2_A14;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC5_C15;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC8_B6;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC8_A8;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC6_C14;
-- Node name is '|lpm_add_sub:73|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ001);
_EQ001 = _LC1_B11 & _LC2_B11;
-- Node name is '|lpm_add_sub:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ002);
_EQ002 = _LC1_B11 & _LC2_B11 & _LC6_B11;
-- Node name is ':23'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ003);
_EQ003 = !_LC4_B11
# !_LC1_B11 & !_LC2_B11 & !_LC6_B11;
-- Node name is ':53'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
_EQ004 = _LC4_B11 & _LC5_B11 & !_LC8_B11
# !_LC4_B11 & _LC5_B11 & _LC8_B11;
-- Node name is ':54'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
_EQ005 = _LC5_B11 & _LC6_B11 & !_LC7_B11
# _LC5_B11 & !_LC6_B11 & _LC7_B11;
-- Node name is ':55'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
_EQ006 = _LC1_B11 & !_LC2_B11 & _LC5_B11
# !_LC1_B11 & _LC2_B11 & _LC5_B11;
-- Node name is ':56'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
_EQ007 = !_LC2_B11 & _LC5_B11;
-- Node name is ':67'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':68'
-- Equation name is '_LC8_A8', type is buried
_LC8_A8 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':69'
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':70'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':71'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':72'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
Project Information e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,440K
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