📄 clkscan1_old.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1_old.rpt
clkscan1_old
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clk
INPUT 1 start
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1_old.rpt
clkscan1_old
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1_old.rpt
clkscan1_old
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is ':58' = 'count0'
-- Equation name is 'count0', location is LC3_C24, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
_EQ001 = !count0 & _LC3_C13;
-- Node name is ':57' = 'count1'
-- Equation name is 'count1', location is LC5_C24, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
_EQ002 = !count0 & count1 & _LC3_C13
# count0 & !count1 & _LC3_C13;
-- Node name is ':56' = 'count2'
-- Equation name is 'count2', location is LC2_C13, type is buried.
count2 = DFFE( _LC1_C13, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
-- Node name is ':55' = 'count3'
-- Equation name is 'count3', location is LC7_C13, type is buried.
count3 = DFFE( _LC6_C13, GLOBAL( clk), GLOBAL(!reset), VCC, enable);
-- Node name is ':53' = 'enable'
-- Equation name is 'enable', location is LC1_C24, type is buried.
enable = DFFE( VCC, GLOBAL( start), GLOBAL(!reset), VCC, VCC);
-- Node name is 'scan_data0'
-- Equation name is 'scan_data0', type is output
scan_data0 = _LC2_C24;
-- Node name is 'scan_data1'
-- Equation name is 'scan_data1', type is output
scan_data1 = _LC6_C24;
-- Node name is 'scan_data2'
-- Equation name is 'scan_data2', type is output
scan_data2 = _LC4_C13;
-- Node name is 'scan_data3'
-- Equation name is 'scan_data3', type is output
scan_data3 = _LC5_C13;
-- Node name is 'scan_en0'
-- Equation name is 'scan_en0', type is output
scan_en0 = _LC7_C1;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC4_B5;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC3_B19;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC8_A16;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC5_B13;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC5_C5;
-- Node name is ':23'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ003);
_EQ003 = !count3
# !count0 & !count1 & !count2;
-- Node name is ':40'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ004);
_EQ004 = count0 & count1 & count2 & !count3
# !count0 & !count1 & !count2 & count3;
-- Node name is ':41'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ005);
_EQ005 = !count1 & count2 & _LC3_C13
# !count0 & count2 & _LC3_C13
# count0 & count1 & !count2 & _LC3_C13;
-- Node name is ':42'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = LCELL( _EQ006);
_EQ006 = !count0 & count1 & _LC3_C13
# count0 & !count1 & _LC3_C13;
-- Node name is ':93'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = enable & _LC6_C13 & !reset
# count3 & !enable & !reset;
-- Node name is ':94'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = enable & _LC1_C13 & !reset
# count2 & !enable & !reset;
-- Node name is ':95'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = enable & _LC4_C24 & !reset
# count1 & !enable & !reset;
-- Node name is ':96'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !count0 & enable & _LC3_C13 & !reset
# count0 & !enable & !reset;
-- Node name is ':103'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':104'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':105'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':106'
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':107'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':108'
-- Equation name is '_LC7_C1', type is buried
_LC7_C1 = DFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
Project Informatione:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan1_old.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,235K
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