📄 clkscan.rpt
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- 4 - B 04 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:201|addcore:adder|:183
- 5 - B 04 AND2 0 4 0 3 |clkdiv:2|lpm_add_sub:201|addcore:adder|:187
- 4 - B 06 AND2 0 3 0 4 |clkdiv:2|lpm_add_sub:201|addcore:adder|:195
- 1 - B 06 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:201|addcore:adder|:203
- 4 - B 09 AND2 0 4 0 2 |clkdiv:2|lpm_add_sub:201|addcore:adder|:207
- 6 - B 09 OR2 0 4 0 23 |clkdiv:2|:12
- 2 - B 06 OR2 0 4 0 2 |clkdiv:2|:27
- 2 - B 04 OR2 s 0 4 0 1 |clkdiv:2|~34~1
- 1 - B 07 OR2 0 4 0 1 |clkdiv:2|:54
- 1 - B 12 OR2 0 4 0 1 |clkdiv:2|:69
- 5 - B 12 AND2 0 3 0 1 |clkdiv:2|:84
- 4 - B 12 OR2 0 3 0 2 |clkdiv:2|:97
- 8 - B 09 DFFE + 0 3 0 2 |clkdiv:2|clk_count22 (|clkdiv:2|:174)
- 5 - B 09 DFFE + 0 2 0 3 |clkdiv:2|clk_count21 (|clkdiv:2|:175)
- 7 - B 09 DFFE + 0 2 0 3 |clkdiv:2|clk_count20 (|clkdiv:2|:176)
- 5 - B 06 DFFE + 0 3 0 3 |clkdiv:2|clk_count19 (|clkdiv:2|:177)
- 6 - B 06 DFFE + 0 2 0 4 |clkdiv:2|clk_count18 (|clkdiv:2|:178)
- 3 - B 06 DFFE + 0 3 0 2 |clkdiv:2|clk_count17 (|clkdiv:2|:179)
- 8 - B 06 DFFE + 0 2 0 3 |clkdiv:2|clk_count16 (|clkdiv:2|:180)
- 6 - B 04 DFFE + 0 2 0 2 |clkdiv:2|clk_count15 (|clkdiv:2|:181)
- 1 - B 04 DFFE + 0 3 0 3 |clkdiv:2|clk_count14 (|clkdiv:2|:182)
- 3 - B 04 DFFE + 0 2 0 4 |clkdiv:2|clk_count13 (|clkdiv:2|:183)
- 6 - B 07 DFFE + 0 2 0 2 |clkdiv:2|clk_count12 (|clkdiv:2|:184)
- 4 - B 07 DFFE + 0 3 0 3 |clkdiv:2|clk_count11 (|clkdiv:2|:185)
- 3 - B 07 DFFE + 0 2 0 4 |clkdiv:2|clk_count10 (|clkdiv:2|:186)
- 8 - B 12 DFFE + 0 3 0 2 |clkdiv:2|clk_count9 (|clkdiv:2|:187)
- 7 - B 12 DFFE + 0 3 0 3 |clkdiv:2|clk_count8 (|clkdiv:2|:188)
- 2 - B 09 DFFE + 0 2 0 4 |clkdiv:2|clk_count7 (|clkdiv:2|:189)
- 6 - B 12 DFFE + 0 2 0 2 |clkdiv:2|clk_count6 (|clkdiv:2|:190)
- 5 - B 03 DFFE + 0 3 0 2 |clkdiv:2|clk_count5 (|clkdiv:2|:191)
- 3 - B 03 DFFE + 0 2 0 3 |clkdiv:2|clk_count4 (|clkdiv:2|:192)
- 7 - B 03 DFFE + 0 2 0 1 |clkdiv:2|clk_count3 (|clkdiv:2|:193)
- 2 - B 03 DFFE + 0 3 0 1 |clkdiv:2|clk_count2 (|clkdiv:2|:194)
- 6 - B 03 DFFE + 0 2 0 2 |clkdiv:2|clk_count1 (|clkdiv:2|:195)
- 4 - B 03 DFFE + 0 1 0 3 |clkdiv:2|clk_count0 (|clkdiv:2|:196)
- 1 - B 09 DFFE + 0 4 0 14 |clkdiv:2|:200
- 7 - B 14 AND2 0 2 0 1 |clkscan1:1|lpm_add_sub:82|addcore:adder|:55
- 6 - B 14 AND2 0 3 0 1 |clkscan1:1|lpm_add_sub:82|addcore:adder|:59
- 2 - B 14 DFFE 0 4 0 2 |clkscan1:1|count3 (|clkscan1:1|:14)
- 1 - B 14 DFFE 0 4 0 3 |clkscan1:1|count2 (|clkscan1:1|:15)
- 3 - B 14 DFFE 0 4 0 4 |clkscan1:1|count1 (|clkscan1:1|:16)
- 8 - B 14 DFFE 0 3 0 5 |clkscan1:1|count0 (|clkscan1:1|:17)
- 5 - B 14 OR2 0 4 0 4 |clkscan1:1|:27
- 4 - B 23 DFFE 0 3 0 16 |clkscan1:1|:61
- 2 - B 23 DFFE 0 3 0 16 |clkscan1:1|:62
- 5 - B 23 DFFE 0 3 0 15 |clkscan1:1|:63
- 4 - B 14 DFFE 0 3 0 16 |clkscan1:1|:64
- 4 - C 04 DFFE 1 1 1 0 |clkscan1:1|:70
- 8 - C 04 DFFE 1 1 1 0 |clkscan1:1|:71
- 6 - C 04 DFFE 1 1 1 0 |clkscan1:1|:72
- 7 - C 04 DFFE 1 1 1 0 |clkscan1:1|:73
- 2 - C 04 DFFE 1 1 1 0 |clkscan1:1|:74
- 1 - C 04 DFFE 1 1 1 0 |clkscan1:1|:75
- 4 - B 16 AND2 0 4 0 2 |p7segment:3|:48
- 7 - B 23 AND2 0 4 0 1 |p7segment:3|:60
- 3 - B 19 AND2 0 4 0 3 |p7segment:3|:144
- 6 - B 16 AND2 0 4 0 1 |p7segment:3|:180
- 3 - B 15 AND2 0 4 0 2 |p7segment:3|:192
- 2 - B 16 OR2 s ! 0 4 0 2 |p7segment:3|~218~1
- 1 - B 15 AND2 s 0 2 0 3 |p7segment:3|~218~2
- 1 - B 19 AND2 ! 0 4 0 7 |p7segment:3|:218
- 2 - B 15 OR2 s ! 0 3 0 2 |p7segment:3|~227~1
- 5 - B 16 OR2 s 0 4 0 1 |p7segment:3|~227~2
- 8 - B 23 OR2 s 0 4 0 1 |p7segment:3|~227~3
- 3 - B 23 OR2 0 3 1 0 |p7segment:3|:227
- 4 - B 19 OR2 s ! 0 4 0 2 |p7segment:3|~230~1
- 5 - B 19 OR2 0 2 1 0 |p7segment:3|:230
- 4 - B 15 OR2 s 0 4 0 2 |p7segment:3|~233~1
- 5 - B 15 OR2 s 0 4 0 1 |p7segment:3|~233~2
- 6 - B 15 OR2 0 3 1 0 |p7segment:3|:233
- 6 - B 19 OR2 s 0 4 0 1 |p7segment:3|~236~1
- 7 - B 19 OR2 s 0 4 0 1 |p7segment:3|~236~2
- 8 - B 19 OR2 s 0 4 0 1 |p7segment:3|~236~3
- 2 - B 19 OR2 0 3 1 0 |p7segment:3|:236
- 8 - B 16 OR2 s 0 4 0 1 |p7segment:3|~239~1
- 1 - B 16 OR2 0 2 1 0 |p7segment:3|:239
- 8 - B 15 OR2 0 3 1 0 |p7segment:3|:242
- 7 - B 16 OR2 s 0 4 0 1 |p7segment:3|~245~1
- 3 - B 16 OR2 s 0 4 0 1 |p7segment:3|~245~2
- 1 - B 23 OR2 s 0 4 0 1 |p7segment:3|~245~3
- 7 - B 15 OR2 0 3 1 0 |p7segment:3|:245
- 1 - B 24 SOFT s ! 1 0 0 4 reset~1
- 6 - B 23 SOFT s ! 1 0 0 4 start~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\verilog hdl\clkscan\clkscan1\clkscan.rpt
clkscan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 7/ 96( 7%) 21/ 48( 43%) 19/ 48( 39%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 1/ 96( 1%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog hdl\clkscan\clkscan1\clkscan.rpt
clkscan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk
DFF 14 |clkdiv:2|:200
Device-Specific Information: f:\verilog hdl\clkscan\clkscan1\clkscan.rpt
clkscan
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 11 reset
INPUT 11 start
Device-Specific Information: f:\verilog hdl\clkscan\clkscan1\clkscan.rpt
clkscan
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'dada0'
-- Equation name is 'dada0', type is output
dada0 = _LC7_B15;
-- Node name is 'dada1'
-- Equation name is 'dada1', type is output
dada1 = _LC8_B15;
-- Node name is 'dada2'
-- Equation name is 'dada2', type is output
dada2 = _LC1_B16;
-- Node name is 'dada3'
-- Equation name is 'dada3', type is output
dada3 = _LC2_B19;
-- Node name is 'dada4'
-- Equation name is 'dada4', type is output
dada4 = _LC6_B15;
-- Node name is 'dada5'
-- Equation name is 'dada5', type is output
dada5 = _LC5_B19;
-- Node name is 'dada6'
-- Equation name is 'dada6', type is output
dada6 = _LC3_B23;
-- Node name is 'PIN_NAMEen0'
-- Equation name is 'PIN_NAMEen0', type is output
PIN_NAMEen0 = _LC1_C4;
-- Node name is 'PIN_NAMEen1'
-- Equation name is 'PIN_NAMEen1', type is output
PIN_NAMEen1 = _LC2_C4;
-- Node name is 'PIN_NAMEen2'
-- Equation name is 'PIN_NAMEen2', type is output
PIN_NAMEen2 = _LC7_C4;
-- Node name is 'PIN_NAMEen3'
-- Equation name is 'PIN_NAMEen3', type is output
PIN_NAMEen3 = _LC6_C4;
-- Node name is 'PIN_NAMEen4'
-- Equation name is 'PIN_NAMEen4', type is output
PIN_NAMEen4 = _LC8_C4;
-- Node name is 'PIN_NAMEen5'
-- Equation name is 'PIN_NAMEen5', type is output
PIN_NAMEen5 = _LC4_C4;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_B24, type is buried.
-- synthesized logic cell
!_LC1_B24 = _LC1_B24~NOT;
_LC1_B24~NOT = LCELL(!reset);
-- Node name is 'start~1'
-- Equation name is 'start~1', location is LC6_B23, type is buried.
-- synthesized logic cell
!_LC6_B23 = _LC6_B23~NOT;
_LC6_B23~NOT = LCELL(!start);
-- Node name is '|clkdiv:2|:196' = '|clkdiv:2|clk_count0'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC4_B3 & _LC6_B9;
-- Node name is '|clkdiv:2|:195' = '|clkdiv:2|clk_count1'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC4_B3 & !_LC6_B3 & _LC6_B9
# !_LC4_B3 & _LC6_B3 & _LC6_B9;
-- Node name is '|clkdiv:2|:194' = '|clkdiv:2|clk_count2'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_B3 & !_LC4_B3 & _LC6_B9
# _LC2_B3 & !_LC6_B3 & _LC6_B9
# !_LC2_B3 & _LC4_B3 & _LC6_B3 & _LC6_B9;
-- Node name is '|clkdiv:2|:193' = '|clkdiv:2|clk_count3'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B3 & _LC6_B9 & _LC7_B3
# _LC1_B3 & _LC6_B9 & !_LC7_B3;
-- Node name is '|clkdiv:2|:192' = '|clkdiv:2|clk_count4'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC3_B3 & _LC6_B9 & !_LC8_B3
# !_LC3_B3 & _LC6_B9 & _LC8_B3;
-- Node name is '|clkdiv:2|:191' = '|clkdiv:2|clk_count5'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC3_B3 & _LC5_B3 & _LC6_B9
# _LC5_B3 & _LC6_B9 & !_LC8_B3
# _LC3_B3 & !_LC5_B3 & _LC6_B9 & _LC8_B3;
-- Node name is '|clkdiv:2|:190' = '|clkdiv:2|clk_count6'
-- Equation name is '_LC6_B12', type is buried
_LC6_B12 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC4_B12 & _LC6_B9 & _LC6_B12
# !_LC4_B12 & _LC6_B9 & !_LC6_B12;
-- Node name is '|clkdiv:2|:189' = '|clkdiv:2|clk_count7'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC2_B9 & !_LC3_B12 & _LC6_B9
# !_LC2_B9 & _LC3_B12 & _LC6_B9;
-- Node name is '|clkdiv:2|:188' = '|clkdiv:2|clk_count8'
-- Equation name is '_LC7_B12', type is buried
_LC7_B12 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC2_B9 & _LC6_B9 & _LC7_B12
# !_LC3_B12 & _LC6_B9 & _LC7_B12
# _LC2_B9 & _LC3_B12 & _LC6_B9 & !_LC7_B12;
-- Node name is '|clkdiv:2|:187' = '|clkdiv:2|clk_count9'
-- Equation name is '_LC8_B12', type is buried
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