📄 clkscan_top.rpt
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-- Node name is '|p7segment:3|:48'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = LCELL( _EQ055);
_EQ055 = !_LC2_B23 & !_LC3_B23 & _LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|:60'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = LCELL( _EQ056);
_EQ056 = _LC2_B23 & !_LC3_B23 & !_LC4_B22 & !_LC6_B22;
-- Node name is '|p7segment:3|:144'
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ057);
_EQ057 = !_LC2_B23 & _LC3_B23 & _LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|:180'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = LCELL( _EQ058);
_EQ058 = _LC2_B23 & _LC3_B23 & !_LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|:192'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = LCELL( _EQ059);
_EQ059 = _LC2_B23 & _LC3_B23 & _LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|~218~1'
-- Equation name is '_LC2_C11', type is buried
-- synthesized logic cell
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL( _EQ060);
_EQ060 = _LC2_B23 & !_LC3_B23 & !_LC4_B22 & _LC6_B22
# _LC2_B23 & !_LC3_B23 & _LC4_B22 & !_LC6_B22;
-- Node name is '|p7segment:3|~218~2'
-- Equation name is '_LC3_C1', type is buried
-- synthesized logic cell
_LC3_C1 = LCELL( _EQ061);
_EQ061 = !_LC1_C6 & !_LC4_C1;
-- Node name is '|p7segment:3|:218'
-- Equation name is '_LC1_C11', type is buried
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ062);
_EQ062 = !_LC2_C9 & _LC2_C11 & _LC3_C1 & !_LC4_C11;
-- Node name is '|p7segment:3|~227~1'
-- Equation name is '_LC4_C1', type is buried
-- synthesized logic cell
!_LC4_C1 = _LC4_C1~NOT;
_LC4_C1~NOT = LCELL( _EQ063);
_EQ063 = !_LC3_B23
# !_LC2_B23
# _LC4_B22;
-- Node name is '|p7segment:3|~227~2'
-- Equation name is '_LC3_C6', type is buried
-- synthesized logic cell
_LC3_C6 = LCELL( _EQ064);
_EQ064 = !_LC2_B23 & _LC3_B23 & !_LC4_B22 & _LC6_B22
# !_LC2_B23 & _LC3_B23 & _LC4_B22 & !_LC6_B22;
-- Node name is '|p7segment:3|~227~3'
-- Equation name is '_LC8_C1', type is buried
-- synthesized logic cell
_LC8_C1 = LCELL( _EQ065);
_EQ065 = !_LC2_B23 & !_LC4_B22
# !_LC2_B23 & _LC3_B23 & !_LC6_B22
# !_LC3_B23 & _LC6_B22
# _LC2_B23 & !_LC3_B23 & _LC4_B22;
-- Node name is '|p7segment:3|:227'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = LCELL( _EQ066);
_EQ066 = _LC1_C1 & !_LC1_C11
# _LC8_C1
# !_LC3_C1;
-- Node name is '|p7segment:3|~230~1'
-- Equation name is '_LC4_C11', type is buried
-- synthesized logic cell
!_LC4_C11 = _LC4_C11~NOT;
_LC4_C11~NOT = LCELL( _EQ067);
_EQ067 = _LC2_B23 & !_LC3_B23 & _LC4_B22 & !_LC6_B22
# _LC2_B23 & _LC3_B23 & !_LC4_B22
# _LC2_B23 & !_LC4_B22 & _LC6_B22
# _LC2_B23 & _LC3_B23 & _LC6_B22
# _LC3_B23 & _LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|:230'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = LCELL( _EQ068);
_EQ068 = !_LC1_C11 & _LC3_C11
# _LC4_C11;
-- Node name is '|p7segment:3|~233~1'
-- Equation name is '_LC6_C1', type is buried
-- synthesized logic cell
_LC6_C1 = LCELL( _EQ069);
_EQ069 = !_LC2_B23 & !_LC4_B22 & !_LC6_B22
# _LC2_B23 & !_LC3_B23 & !_LC4_B22
# _LC2_B23 & !_LC3_B23 & !_LC6_B22
# !_LC3_B23 & !_LC4_B22 & !_LC6_B22
# !_LC2_B23 & _LC3_B23;
-- Node name is '|p7segment:3|~233~2'
-- Equation name is '_LC7_C1', type is buried
-- synthesized logic cell
_LC7_C1 = LCELL( _EQ070);
_EQ070 = !_LC3_B23 & _LC4_B22 & _LC6_B22
# !_LC2_B23 & !_LC3_B23 & _LC4_B22
# _LC2_B23 & _LC3_B23 & _LC4_B22 & !_LC6_B22;
-- Node name is '|p7segment:3|:233'
-- Equation name is '_LC5_C1', type is buried
_LC5_C1 = LCELL( _EQ071);
_EQ071 = !_LC1_C11 & _LC5_C1
# _LC7_C1
# _LC6_C1;
-- Node name is '|p7segment:3|~236~1'
-- Equation name is '_LC5_C9', type is buried
-- synthesized logic cell
_LC5_C9 = LCELL( _EQ072);
_EQ072 = !_LC2_B23 & _LC3_B23 & _LC4_B22 & !_LC6_B22
# _LC2_B23 & !_LC3_B23 & _LC4_B22 & !_LC6_B22;
-- Node name is '|p7segment:3|~236~2'
-- Equation name is '_LC6_C9', type is buried
-- synthesized logic cell
_LC6_C9 = LCELL( _EQ073);
_EQ073 = !_LC2_B23 & !_LC4_B22 & !_LC6_B22
# !_LC2_B23 & !_LC3_B23 & !_LC4_B22
# _LC2_B23 & _LC3_B23 & _LC4_B22 & !_LC6_B22
# !_LC3_B23 & !_LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|~236~3'
-- Equation name is '_LC8_C9', type is buried
-- synthesized logic cell
_LC8_C9 = LCELL( _EQ074);
_EQ074 = _LC5_C9
# _LC6_C9
# _LC4_C1
# _LC2_C9;
-- Node name is '|p7segment:3|:236'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = LCELL( _EQ075);
_EQ075 = !_LC1_C11 & _LC7_C9
# _LC8_C9
# _LC3_C9;
-- Node name is '|p7segment:3|~239~1'
-- Equation name is '_LC4_C9', type is buried
-- synthesized logic cell
_LC4_C9 = LCELL( _EQ076);
_EQ076 = _LC3_B23 & _LC6_B22
# _LC3_B23 & !_LC4_B22
# !_LC2_B23 & !_LC4_B22
# _LC2_B23 & _LC3_B23
# !_LC4_B22 & _LC6_B22;
-- Node name is '|p7segment:3|:239'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ077);
_EQ077 = _LC1_C9 & !_LC1_C11
# _LC4_C9;
-- Node name is '|p7segment:3|:242'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ078);
_EQ078 = !_LC1_C11 & _LC2_C1
# _LC6_C1
# !_LC3_C1;
-- Node name is '|p7segment:3|~245~1'
-- Equation name is '_LC6_C6', type is buried
-- synthesized logic cell
_LC6_C6 = LCELL( _EQ079);
_EQ079 = !_LC2_B23 & _LC3_B23 & !_LC4_B22 & !_LC6_B22
# !_LC2_B23 & !_LC3_B23 & !_LC4_B22 & _LC6_B22
# _LC2_B23 & _LC3_B23 & _LC4_B22 & !_LC6_B22;
-- Node name is '|p7segment:3|~245~2'
-- Equation name is '_LC7_C6', type is buried
-- synthesized logic cell
_LC7_C6 = LCELL( _EQ080);
_EQ080 = !_LC2_C11
# _LC3_C6
# _LC5_C6
# _LC6_C6;
-- Node name is '|p7segment:3|~245~3'
-- Equation name is '_LC8_C6', type is buried
-- synthesized logic cell
_LC8_C6 = LCELL( _EQ081);
_EQ081 = _LC3_C9
# _LC2_C9
# _LC2_C6
# _LC7_C6;
-- Node name is '|p7segment:3|:245'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = LCELL( _EQ082);
_EQ082 = !_LC1_C11 & _LC4_C6
# _LC1_C6
# _LC8_C6;
Project Informatione:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan_top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,524K
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