📄 clkscan_top.rpt
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Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan_top.rpt
clkscan_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 05 OR2 ! 0 3 0 2 |clkdiv:2|lpm_add_sub:201|addcore:adder|:135
- 2 - B 05 OR2 ! 0 2 0 4 |clkdiv:2|lpm_add_sub:201|addcore:adder|:139
- 1 - B 04 AND2 0 4 0 4 |clkdiv:2|lpm_add_sub:201|addcore:adder|:151
- 2 - B 07 AND2 0 2 0 1 |clkdiv:2|lpm_add_sub:201|addcore:adder|:155
- 5 - B 04 AND2 0 4 0 4 |clkdiv:2|lpm_add_sub:201|addcore:adder|:163
- 4 - B 06 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:201|addcore:adder|:171
- 1 - B 06 AND2 0 4 0 4 |clkdiv:2|lpm_add_sub:201|addcore:adder|:175
- 4 - B 10 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:201|addcore:adder|:183
- 8 - B 10 AND2 0 4 0 3 |clkdiv:2|lpm_add_sub:201|addcore:adder|:187
- 1 - B 07 AND2 0 3 0 4 |clkdiv:2|lpm_add_sub:201|addcore:adder|:195
- 5 - B 12 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:201|addcore:adder|:203
- 2 - B 12 AND2 0 4 0 2 |clkdiv:2|lpm_add_sub:201|addcore:adder|:207
- 6 - B 12 OR2 0 4 0 23 |clkdiv:2|:12
- 8 - B 07 OR2 0 4 0 2 |clkdiv:2|:27
- 1 - B 10 OR2 s 0 4 0 1 |clkdiv:2|~34~1
- 2 - B 06 OR2 0 4 0 1 |clkdiv:2|:54
- 2 - B 04 OR2 0 4 0 1 |clkdiv:2|:69
- 4 - B 04 AND2 0 3 0 1 |clkdiv:2|:84
- 3 - B 04 OR2 0 3 0 2 |clkdiv:2|:97
- 8 - B 12 DFFE + 0 3 0 2 |clkdiv:2|clk_count22 (|clkdiv:2|:174)
- 3 - B 12 DFFE + 0 2 0 3 |clkdiv:2|clk_count21 (|clkdiv:2|:175)
- 7 - B 12 DFFE + 0 2 0 3 |clkdiv:2|clk_count20 (|clkdiv:2|:176)
- 4 - B 12 DFFE + 0 3 0 3 |clkdiv:2|clk_count19 (|clkdiv:2|:177)
- 4 - B 07 DFFE + 0 2 0 4 |clkdiv:2|clk_count18 (|clkdiv:2|:178)
- 6 - B 07 DFFE + 0 3 0 2 |clkdiv:2|clk_count17 (|clkdiv:2|:179)
- 5 - B 07 DFFE + 0 2 0 3 |clkdiv:2|clk_count16 (|clkdiv:2|:180)
- 5 - B 10 DFFE + 0 2 0 2 |clkdiv:2|clk_count15 (|clkdiv:2|:181)
- 3 - B 10 DFFE + 0 3 0 3 |clkdiv:2|clk_count14 (|clkdiv:2|:182)
- 2 - B 10 DFFE + 0 2 0 4 |clkdiv:2|clk_count13 (|clkdiv:2|:183)
- 6 - B 06 DFFE + 0 2 0 2 |clkdiv:2|clk_count12 (|clkdiv:2|:184)
- 3 - B 06 DFFE + 0 3 0 3 |clkdiv:2|clk_count11 (|clkdiv:2|:185)
- 5 - B 06 DFFE + 0 2 0 4 |clkdiv:2|clk_count10 (|clkdiv:2|:186)
- 8 - B 04 DFFE + 0 3 0 2 |clkdiv:2|clk_count9 (|clkdiv:2|:187)
- 7 - B 04 DFFE + 0 3 0 3 |clkdiv:2|clk_count8 (|clkdiv:2|:188)
- 3 - B 07 DFFE + 0 2 0 4 |clkdiv:2|clk_count7 (|clkdiv:2|:189)
- 6 - B 04 DFFE + 0 2 0 2 |clkdiv:2|clk_count6 (|clkdiv:2|:190)
- 5 - B 05 DFFE + 0 3 0 2 |clkdiv:2|clk_count5 (|clkdiv:2|:191)
- 3 - B 05 DFFE + 0 2 0 3 |clkdiv:2|clk_count4 (|clkdiv:2|:192)
- 8 - B 05 DFFE + 0 2 0 1 |clkdiv:2|clk_count3 (|clkdiv:2|:193)
- 4 - B 05 DFFE + 0 3 0 1 |clkdiv:2|clk_count2 (|clkdiv:2|:194)
- 7 - B 05 DFFE + 0 2 0 2 |clkdiv:2|clk_count1 (|clkdiv:2|:195)
- 6 - B 05 DFFE + 0 1 0 3 |clkdiv:2|clk_count0 (|clkdiv:2|:196)
- 1 - B 12 DFFE + 0 4 0 14 |clkdiv:2|:200
- 4 - B 23 AND2 0 2 0 1 |clkscan1:1|lpm_add_sub:109|addcore:adder|:55
- 1 - B 23 OR2 0 4 0 6 |clkscan1:1|:23
- 5 - B 23 OR2 0 4 0 2 |clkscan1:1|:40
- 7 - B 23 OR2 0 4 0 2 |clkscan1:1|:41
- 7 - B 22 OR2 0 3 0 1 |clkscan1:1|:42
- 5 - B 22 DFFE + 0 0 0 8 |clkscan1:1|enable (|clkscan1:1|:53)
- 6 - B 23 DFFE 0 3 0 3 |clkscan1:1|count3 (|clkscan1:1|:55)
- 8 - B 23 DFFE 0 3 0 4 |clkscan1:1|count2 (|clkscan1:1|:56)
- 1 - B 22 DFFE 0 4 0 5 |clkscan1:1|count1 (|clkscan1:1|:57)
- 2 - B 22 DFFE 0 3 0 6 |clkscan1:1|count0 (|clkscan1:1|:58)
- 3 - B 23 DFFE 1 4 0 16 |clkscan1:1|:93
- 2 - B 23 DFFE 1 4 0 16 |clkscan1:1|:94
- 6 - B 22 DFFE 1 4 0 15 |clkscan1:1|:95
- 4 - B 22 DFFE 1 4 0 16 |clkscan1:1|:96
- 1 - B 02 DFFE 0 1 1 0 |clkscan1:1|:103
- 2 - B 02 DFFE 0 1 1 0 |clkscan1:1|:104
- 3 - B 22 DFFE 0 1 1 0 |clkscan1:1|:105
- 1 - B 24 DFFE 0 1 1 0 |clkscan1:1|:106
- 8 - B 24 DFFE 0 1 1 0 |clkscan1:1|:107
- 5 - B 24 DFFE 0 1 1 0 |clkscan1:1|:108
- 3 - C 09 AND2 0 4 0 2 |p7segment:3|:48
- 2 - C 06 AND2 0 4 0 1 |p7segment:3|:60
- 2 - C 09 AND2 0 4 0 3 |p7segment:3|:144
- 5 - C 06 AND2 0 4 0 1 |p7segment:3|:180
- 1 - C 06 AND2 0 4 0 2 |p7segment:3|:192
- 2 - C 11 OR2 s ! 0 4 0 2 |p7segment:3|~218~1
- 3 - C 01 AND2 s 0 2 0 3 |p7segment:3|~218~2
- 1 - C 11 AND2 ! 0 4 0 7 |p7segment:3|:218
- 4 - C 01 OR2 s ! 0 3 0 2 |p7segment:3|~227~1
- 3 - C 06 OR2 s 0 4 0 1 |p7segment:3|~227~2
- 8 - C 01 OR2 s 0 4 0 1 |p7segment:3|~227~3
- 1 - C 01 OR2 0 3 1 0 |p7segment:3|:227
- 4 - C 11 OR2 s ! 0 4 0 2 |p7segment:3|~230~1
- 3 - C 11 OR2 0 2 1 0 |p7segment:3|:230
- 6 - C 01 OR2 s 0 4 0 2 |p7segment:3|~233~1
- 7 - C 01 OR2 s 0 4 0 1 |p7segment:3|~233~2
- 5 - C 01 OR2 0 3 1 0 |p7segment:3|:233
- 5 - C 09 OR2 s 0 4 0 1 |p7segment:3|~236~1
- 6 - C 09 OR2 s 0 4 0 1 |p7segment:3|~236~2
- 8 - C 09 OR2 s 0 4 0 1 |p7segment:3|~236~3
- 7 - C 09 OR2 0 3 1 0 |p7segment:3|:236
- 4 - C 09 OR2 s 0 4 0 1 |p7segment:3|~239~1
- 1 - C 09 OR2 0 2 1 0 |p7segment:3|:239
- 2 - C 01 OR2 0 3 1 0 |p7segment:3|:242
- 6 - C 06 OR2 s 0 4 0 1 |p7segment:3|~245~1
- 7 - C 06 OR2 s 0 4 0 1 |p7segment:3|~245~2
- 8 - C 06 OR2 s 0 4 0 1 |p7segment:3|~245~3
- 4 - C 06 OR2 0 3 1 0 |p7segment:3|:245
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan_top.rpt
clkscan_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 23/ 48( 47%) 4/ 48( 8%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 4/ 96( 4%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan_top.rpt
clkscan_top
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk
DFF 14 |clkdiv:2|:200
INPUT 1 start
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan_top.rpt
clkscan_top
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan1\clkscan_top.rpt
clkscan_top
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC4_C6;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC2_C1;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC1_C9;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC7_C9;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC5_C1;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC3_C11;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC1_C1;
-- Node name is 'scan_en0'
-- Equation name is 'scan_en0', type is output
scan_en0 = _LC5_B24;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC8_B24;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC1_B24;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC3_B22;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC2_B2;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC1_B2;
-- Node name is '|clkdiv:2|:196' = '|clkdiv:2|clk_count0'
-- Equation name is '_LC6_B5', type is buried
_LC6_B5 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC6_B5 & _LC6_B12;
-- Node name is '|clkdiv:2|:195' = '|clkdiv:2|clk_count1'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC6_B5 & _LC6_B12 & !_LC7_B5
# !_LC6_B5 & _LC6_B12 & _LC7_B5;
-- Node name is '|clkdiv:2|:194' = '|clkdiv:2|clk_count2'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC4_B5 & !_LC6_B5 & _LC6_B12
# _LC4_B5 & _LC6_B12 & !_LC7_B5
# !_LC4_B5 & _LC6_B5 & _LC6_B12 & _LC7_B5;
-- Node name is '|clkdiv:2|:193' = '|clkdiv:2|clk_count3'
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B5 & _LC6_B12 & _LC8_B5
# _LC1_B5 & _LC6_B12 & !_LC8_B5;
-- Node name is '|clkdiv:2|:192' = '|clkdiv:2|clk_count4'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_B5 & _LC3_B5 & _LC6_B12
# _LC2_B5 & !_LC3_B5 & _LC6_B12;
-- Node name is '|clkdiv:2|:191' = '|clkdiv:2|clk_count5'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC3_B5 & _LC5_B5 & _LC6_B12
# !_LC2_B5 & _LC5_B5 & _LC6_B12
# _LC2_B5 & _LC3_B5 & !_LC5_B5 & _LC6_B12;
-- Node name is '|clkdiv:2|:190' = '|clkdiv:2|clk_count6'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC3_B4 & _LC6_B4 & _LC6_B12
# !_LC3_B4 & !_LC6_B4 & _LC6_B12;
-- Node name is '|clkdiv:2|:189' = '|clkdiv:2|clk_count7'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC1_B4 & _LC3_B7 & _LC6_B12
# _LC1_B4 & !_LC3_B7 & _LC6_B12;
-- Node name is '|clkdiv:2|:188' = '|clkdiv:2|clk_count8'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC3_B7 & _LC6_B12 & _LC7_B4
# !_LC1_B4 & _LC6_B12 & _LC7_B4
# _LC1_B4 & _LC3_B7 & _LC6_B12 & !_LC7_B4;
-- Node name is '|clkdiv:2|:187' = '|clkdiv:2|clk_count9'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC6_B12 & !_LC7_B4 & _LC8_B4
# !_LC2_B7 & _LC6_B12 & _LC8_B4
# _LC2_B7 & _LC6_B12 & _LC7_B4 & !_LC8_B4;
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