timer.rpt

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

_LC6_A18 = LCELL( _EQ020);
  _EQ020 = !_LC2_A18 &  started
         #  _LC3_A18 &  started;

-- Node name is '~120~1' 
-- Equation name is '~120~1', location is LC8_A22, type is buried.
-- synthesized logic cell 
_LC8_A22 = LCELL( _EQ021);
  _EQ021 = !_LC3_A21 &  _LC6_A18;

-- Node name is '~129~1' 
-- Equation name is '~129~1', location is LC2_A21, type is buried.
-- synthesized logic cell 
_LC2_A21 = LCELL( _EQ022);
  _EQ022 = !reset & !started;

-- Node name is '~136~1' 
-- Equation name is '~136~1', location is LC5_A18, type is buried.
-- synthesized logic cell 
_LC5_A18 = LCELL( _EQ023);
  _EQ023 =  _LC2_A18 &  _LC8_A22 & !reset
         #  _LC2_A18 & !reset & !started;

-- Node name is ':141' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = DFFE( _EQ024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ024 =  _LC6_A18 &  _LC7_A18
         #  _LC8_A18 & !started;

-- Node name is ':142' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = DFFE( _EQ025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ025 =  _LC6_A13 &  _LC6_A18
         #  _LC7_A13 & !started;

-- Node name is ':143' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = DFFE( _EQ026, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ026 =  _LC1_A13 &  _LC6_A18
         #  _LC2_A13 & !started;

-- Node name is ':144' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = DFFE( _EQ027, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ027 = !_LC2_A18 &  _LC3_A21 &  _LC6_A18
         #  _LC5_A18;

-- Node name is ':145' 
-- Equation name is '_LC7_A21', type is buried 
_LC7_A21 = DFFE( _EQ028, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ028 =  _LC7_A21 & !_LC8_A21 &  _LC8_A22
         # !_LC7_A21 &  _LC8_A21 &  _LC8_A22
         #  _LC2_A21 &  _LC7_A21;

-- Node name is ':146' 
-- Equation name is '_LC1_A21', type is buried 
_LC1_A21 = DFFE( _EQ029, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ029 =  _LC1_A21 & !_LC6_A21 &  _LC8_A22
         # !_LC1_A21 &  _LC6_A21 &  _LC8_A22
         #  _LC1_A21 &  _LC2_A21;

-- Node name is ':147' 
-- Equation name is '_LC4_A21', type is buried 
_LC4_A21 = DFFE( _EQ030, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ030 =  _LC4_A21 & !_LC5_A21 &  _LC8_A22
         # !_LC4_A21 &  _LC5_A21 &  _LC8_A22
         #  _LC2_A21 &  _LC4_A21;

-- Node name is ':148' 
-- Equation name is '_LC5_A21', type is buried 
_LC5_A21 = DFFE( _EQ031, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ031 = !_LC5_A21 &  started
         #  _LC2_A21 &  _LC5_A21;

-- Node name is '~155~1' 
-- Equation name is '~155~1', location is LC4_C14, type is buried.
-- synthesized logic cell 
!_LC4_C14 = _LC4_C14~NOT;
_LC4_C14~NOT = LCELL( _EQ032);
  _EQ032 = !_LC2_C14 & !_LC5_C14 &  _LC6_C14;

-- Node name is ':155' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = LCELL( _EQ033);
  _EQ033 =  _LC1_C16 &  _LC3_C14 & !_LC4_C14;

-- Node name is ':167' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = LCELL( _EQ034);
  _EQ034 = !_LC2_C16 &  _LC3_C16 &  _LC4_C16 & !_LC6_C16;

-- Node name is '~202~1' 
-- Equation name is '~202~1', location is LC5_C16, type is buried.
-- synthesized logic cell 
_LC5_C16 = LCELL( _EQ035);
  _EQ035 = !_LC1_C14 & !_LC1_C16;

-- Node name is ':214' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = DFFE( _EQ036,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ036 = !_LC1_C14 &  _LC2_C14 & !_LC8_C14
         # !_LC1_C14 &  _LC1_C16 & !_LC2_C14 &  _LC8_C14
         # !_LC1_C14 & !_LC1_C16 &  _LC2_C14;

-- Node name is ':215' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = DFFE( _EQ037,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ037 = !_LC1_C14 &  _LC6_C14 & !_LC7_C14
         # !_LC1_C14 &  _LC1_C16 & !_LC6_C14 &  _LC7_C14
         # !_LC1_C14 & !_LC1_C16 &  _LC6_C14;

-- Node name is ':216' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = DFFE( _EQ038,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ038 = !_LC1_C14 & !_LC3_C14 &  _LC5_C14
         # !_LC1_C14 &  _LC1_C16 &  _LC3_C14 & !_LC5_C14
         # !_LC1_C14 & !_LC1_C16 &  _LC5_C14;

-- Node name is ':217' 
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = DFFE( _EQ039,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ039 = !_LC1_C14 & !_LC1_C16 &  _LC3_C14
         # !_LC1_C14 &  _LC1_C16 & !_LC3_C14;

-- Node name is ':218' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = DFFE( _EQ040,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ040 =  _LC3_C16 &  _LC5_C16 & !_LC7_C16
         # !_LC2_C16 &  _LC3_C16 &  _LC5_C16
         #  _LC2_C16 & !_LC3_C16 &  _LC5_C16 &  _LC7_C16;

-- Node name is ':219' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = DFFE( _EQ041,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ041 =  _LC2_C16 &  _LC5_C16 & !_LC6_C16
         #  _LC2_C16 & !_LC4_C16 &  _LC5_C16
         # !_LC2_C16 &  _LC4_C16 &  _LC5_C16 &  _LC6_C16;

-- Node name is ':220' 
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = DFFE( _EQ042,  min_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ042 = !_LC4_C16 &  _LC5_C16 &  _LC6_C16
         #  _LC4_C16 &  _LC5_C16 & !_LC6_C16;

-- Node name is ':221' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = DFFE(!_LC4_C16,  min_clk, GLOBAL(!reset),  VCC,  VCC);

-- Node name is '~227~1' 
-- Equation name is '~227~1', location is LC6_C6, type is buried.
-- synthesized logic cell 
_LC6_C6  = LCELL( _EQ043);
  _EQ043 =  _LC1_C6
         #  _LC5_C11
         #  _LC3_C6;

-- Node name is '~227~2' 
-- Equation name is '~227~2', location is LC3_C11, type is buried.
-- synthesized logic cell 
_LC3_C11 = LCELL( _EQ044);
  _EQ044 =  _LC1_C11
         # !_LC7_C11
         #  _LC2_C11;

-- Node name is ':227' 
-- Equation name is '_LC5_C6', type is buried 
!_LC5_C6 = _LC5_C6~NOT;
_LC5_C6~NOT = LCELL( _EQ045);
  _EQ045 =  _LC4_C6
         # !_LC7_C6
         #  _LC6_C6
         #  _LC3_C11;

-- Node name is ':239' 
-- Equation name is '_LC2_C6', type is buried 
!_LC2_C6 = _LC2_C6~NOT;
_LC2_C6~NOT = LCELL( _EQ046);
  _EQ046 =  _LC7_C6
         # !_LC3_C6
         #  _LC1_C6
         # !_LC4_C6;

-- Node name is '~274~1' 
-- Equation name is '~274~1', location is LC6_C11, type is buried.
-- synthesized logic cell 
_LC6_C11 = LCELL( _EQ047);
  _EQ047 = !_LC2_C6 & !_LC5_C6;

-- Node name is ':286' 
-- Equation name is '_LC5_C11', type is buried 
_LC5_C11 = DFFE( _EQ048,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ048 = !_LC5_C6 &  _LC5_C11 & !_LC8_C11
         #  _LC2_C6 & !_LC5_C6 & !_LC5_C11 &  _LC8_C11
         # !_LC2_C6 & !_LC5_C6 &  _LC5_C11;

-- Node name is ':287' 
-- Equation name is '_LC1_C11', type is buried 
_LC1_C11 = DFFE( _EQ049,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ049 =  _LC1_C11 & !_LC4_C11 & !_LC5_C6
         # !_LC1_C11 &  _LC2_C6 &  _LC4_C11 & !_LC5_C6
         #  _LC1_C11 & !_LC2_C6 & !_LC5_C6;

-- Node name is ':288' 
-- Equation name is '_LC7_C11', type is buried 
_LC7_C11 = DFFE( _EQ050,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ050 = !_LC2_C11 & !_LC5_C6 &  _LC7_C11
         #  _LC2_C6 &  _LC2_C11 & !_LC5_C6 & !_LC7_C11
         # !_LC2_C6 & !_LC5_C6 &  _LC7_C11;

-- Node name is ':289' 
-- Equation name is '_LC2_C11', type is buried 
_LC2_C11 = DFFE( _EQ051,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ051 = !_LC2_C6 &  _LC2_C11 & !_LC5_C6
         #  _LC2_C6 & !_LC2_C11 & !_LC5_C6;

-- Node name is ':290' 
-- Equation name is '_LC3_C6', type is buried 
_LC3_C6  = DFFE( _EQ052,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ052 =  _LC3_C6 &  _LC6_C11 & !_LC8_C6
         #  _LC3_C6 &  _LC6_C11 & !_LC7_C6
         # !_LC3_C6 &  _LC6_C11 &  _LC7_C6 &  _LC8_C6;

-- Node name is ':291' 
-- Equation name is '_LC7_C6', type is buried 
_LC7_C6  = DFFE( _EQ053,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ053 = !_LC1_C6 &  _LC6_C11 &  _LC7_C6
         # !_LC4_C6 &  _LC6_C11 &  _LC7_C6
         #  _LC1_C6 &  _LC4_C6 &  _LC6_C11 & !_LC7_C6;

-- Node name is ':292' 
-- Equation name is '_LC1_C6', type is buried 
_LC1_C6  = DFFE( _EQ054,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ054 =  _LC1_C6 & !_LC4_C6 &  _LC6_C11
         # !_LC1_C6 &  _LC4_C6 &  _LC6_C11;

-- Node name is ':293' 
-- Equation name is '_LC4_C6', type is buried 
_LC4_C6  = DFFE( _EQ055,  h_clk, GLOBAL(!reset),  VCC,  VCC);
  _EQ055 = !_LC4_C6 & !_LC5_C6;

-- Node name is ':297' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = DFFE( _LC5_C6,  h_clk,  VCC,  VCC, !_LC2_C1);



Project Information      e:\amj\eda\2003\experiment\clkscan\clkscan3\timer.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,655K