📄 timer.rpt
字号:
- 1 - A 21 DFFE + 0 3 1 2 :146
- 4 - A 21 DFFE + 0 3 1 3 :147
- 5 - A 21 DFFE + 0 2 1 4 :148
- 4 - A 18 DFFE + 0 3 0 9 min_clk (:153)
- 4 - C 14 AND2 s ! 0 3 0 1 ~155~1
- 1 - C 14 AND2 0 3 0 6 :155
- 1 - C 16 AND2 0 4 0 6 :167
- 5 - C 16 AND2 s 0 2 0 3 ~202~1
- 2 - C 14 DFFE 0 4 1 1 :214
- 6 - C 14 DFFE 0 4 1 2 :215
- 5 - C 14 DFFE 0 4 1 3 :216
- 3 - C 14 DFFE 0 3 1 4 :217
- 3 - C 16 DFFE 0 4 1 1 :218
- 2 - C 16 DFFE 0 4 1 2 :219
- 6 - C 16 DFFE 0 3 1 3 :220
- 4 - C 16 DFFE 0 1 1 4 :221
- 1 - C 01 DFFE 0 3 0 9 h_clk (:225)
- 6 - C 06 OR2 s 0 3 0 1 ~227~1
- 3 - C 11 OR2 s 0 3 0 1 ~227~2
- 5 - C 06 OR2 ! 0 4 0 7 :227
- 2 - C 06 OR2 ! 0 4 0 5 :239
- 6 - C 11 AND2 s 0 2 0 3 ~274~1
- 5 - C 11 DFFE 0 4 1 1 :286
- 1 - C 11 DFFE 0 4 1 2 :287
- 7 - C 11 DFFE 0 4 1 3 :288
- 2 - C 11 DFFE 0 3 1 4 :289
- 3 - C 06 DFFE 0 4 1 2 :290
- 7 - C 06 DFFE 0 4 1 3 :291
- 1 - C 06 DFFE 0 3 1 4 :292
- 4 - C 06 DFFE 0 2 1 5 :293
- 5 - C 01 DFFE 0 3 1 0 :297
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\timer.rpt
timer
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 12/ 48( 25%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 4/ 96( 4%) 8/ 48( 16%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\timer.rpt
timer
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk
DFF 9 min_clk
DFF 9 h_clk
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\timer.rpt
timer
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 26 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\timer.rpt
timer
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'day'
-- Equation name is 'day', type is output
day = _LC5_C1;
-- Node name is ':225' = 'h_clk'
-- Equation name is 'h_clk', location is LC1_C1, type is buried.
h_clk = DFFE( _LC1_C14, min_clk, VCC, VCC, !_LC2_C1);
-- Node name is 'hour0'
-- Equation name is 'hour0', type is output
hour0 = _LC4_C6;
-- Node name is 'hour1'
-- Equation name is 'hour1', type is output
hour1 = _LC1_C6;
-- Node name is 'hour2'
-- Equation name is 'hour2', type is output
hour2 = _LC7_C6;
-- Node name is 'hour3'
-- Equation name is 'hour3', type is output
hour3 = _LC3_C6;
-- Node name is 'hour4'
-- Equation name is 'hour4', type is output
hour4 = _LC2_C11;
-- Node name is 'hour5'
-- Equation name is 'hour5', type is output
hour5 = _LC7_C11;
-- Node name is 'hour6'
-- Equation name is 'hour6', type is output
hour6 = _LC1_C11;
-- Node name is 'hour7'
-- Equation name is 'hour7', type is output
hour7 = _LC5_C11;
-- Node name is ':153' = 'min_clk'
-- Equation name is 'min_clk', location is LC4_A18, type is buried.
min_clk = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, started);
_EQ001 = _LC2_A18 & !_LC3_A18;
-- Node name is 'min0'
-- Equation name is 'min0', type is output
min0 = _LC4_C16;
-- Node name is 'min1'
-- Equation name is 'min1', type is output
min1 = _LC6_C16;
-- Node name is 'min2'
-- Equation name is 'min2', type is output
min2 = _LC2_C16;
-- Node name is 'min3'
-- Equation name is 'min3', type is output
min3 = _LC3_C16;
-- Node name is 'min4'
-- Equation name is 'min4', type is output
min4 = _LC3_C14;
-- Node name is 'min5'
-- Equation name is 'min5', type is output
min5 = _LC5_C14;
-- Node name is 'min6'
-- Equation name is 'min6', type is output
min6 = _LC6_C14;
-- Node name is 'min7'
-- Equation name is 'min7', type is output
min7 = _LC2_C14;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC2_C1, type is buried.
-- synthesized logic cell
!_LC2_C1 = _LC2_C1~NOT;
_LC2_C1~NOT = LCELL(!reset);
-- Node name is 'sec0'
-- Equation name is 'sec0', type is output
sec0 = _LC5_A21;
-- Node name is 'sec1'
-- Equation name is 'sec1', type is output
sec1 = _LC4_A21;
-- Node name is 'sec2'
-- Equation name is 'sec2', type is output
sec2 = _LC1_A21;
-- Node name is 'sec3'
-- Equation name is 'sec3', type is output
sec3 = _LC7_A21;
-- Node name is 'sec4'
-- Equation name is 'sec4', type is output
sec4 = _LC2_A18;
-- Node name is 'sec5'
-- Equation name is 'sec5', type is output
sec5 = _LC8_A13;
-- Node name is 'sec6'
-- Equation name is 'sec6', type is output
sec6 = _LC5_A13;
-- Node name is 'sec7'
-- Equation name is 'sec7', type is output
sec7 = _LC1_A18;
-- Node name is ':30' = 'started'
-- Equation name is 'started', location is LC1_A19, type is buried.
started = DFFE( VCC, GLOBAL( clk), GLOBAL(!reset), GLOBAL(!start), start);
-- Node name is '|lpm_add_sub:299|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ002);
_EQ002 = _LC2_A18 & _LC8_A13;
-- Node name is '|lpm_add_sub:299|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ003);
_EQ003 = _LC2_A18 & _LC5_A13 & _LC8_A13;
-- Node name is '|lpm_add_sub:300|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = LCELL( _EQ004);
_EQ004 = _LC4_A21 & _LC5_A21;
-- Node name is '|lpm_add_sub:300|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ005);
_EQ005 = _LC1_A21 & _LC4_A21 & _LC5_A21;
-- Node name is '|lpm_add_sub:301|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ006);
_EQ006 = _LC3_C14 & _LC5_C14;
-- Node name is '|lpm_add_sub:301|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = LCELL( _EQ007);
_EQ007 = _LC3_C14 & _LC5_C14 & _LC6_C14;
-- Node name is '|lpm_add_sub:302|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ008);
_EQ008 = _LC4_C16 & _LC6_C16;
-- Node name is '|lpm_add_sub:303|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = LCELL( _EQ009);
_EQ009 = _LC2_C11 & _LC7_C11;
-- Node name is '|lpm_add_sub:303|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C11', type is buried
_LC8_C11 = LCELL( _EQ010);
_EQ010 = _LC1_C11 & _LC2_C11 & _LC7_C11;
-- Node name is '|lpm_add_sub:304|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = LCELL( _EQ011);
_EQ011 = _LC1_C6 & _LC4_C6;
-- Node name is '~32~1'
-- Equation name is '~32~1', location is LC3_A18, type is buried.
-- synthesized logic cell
!_LC3_A18 = _LC3_A18~NOT;
_LC3_A18~NOT = LCELL( _EQ012);
_EQ012 = !_LC1_A18 & _LC3_A21 & _LC5_A13 & !_LC8_A13;
-- Node name is ':44'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = LCELL( _EQ013);
_EQ013 = _LC1_A18 & !reset;
-- Node name is ':45'
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ014);
_EQ014 = _LC5_A13 & !reset;
-- Node name is ':46'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ015);
_EQ015 = _LC8_A13 & !reset;
-- Node name is ':69'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ016);
_EQ016 = !_LC1_A21 & !_LC4_A21 & _LC5_A21 & _LC7_A21;
-- Node name is ':92'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = LCELL( _EQ017);
_EQ017 = _LC1_A18 & !_LC3_A13 & _LC3_A21
# !_LC1_A18 & _LC3_A13 & _LC3_A21
# _LC1_A18 & !_LC3_A21 & !reset;
-- Node name is ':93'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ018);
_EQ018 = _LC3_A21 & !_LC4_A13 & _LC5_A13
# _LC3_A21 & _LC4_A13 & !_LC5_A13
# !_LC3_A21 & _LC5_A13 & !reset;
-- Node name is ':94'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ019);
_EQ019 = !_LC2_A18 & _LC3_A21 & _LC8_A13
# _LC2_A18 & _LC3_A21 & !_LC8_A13
# !_LC3_A21 & _LC8_A13 & !reset;
-- Node name is '~116~1'
-- Equation name is '~116~1', location is LC6_A18, type is buried.
-- synthesized logic cell
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