top2.rpt

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

-- Node name is '|clkdiv:5|:183' = '|clkdiv:5|clk_count13' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = DFFE( _EQ042, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ042 =  _LC2_C17 & !_LC2_C22 &  _LC4_C22
         #  _LC2_C17 &  _LC2_C22 & !_LC4_C22;

-- Node name is '|clkdiv:5|:182' = '|clkdiv:5|clk_count14' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = DFFE( _EQ043, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ043 =  _LC2_C17 &  _LC4_C13 & !_LC4_C22
         #  _LC2_C17 & !_LC2_C22 &  _LC4_C13
         #  _LC2_C17 &  _LC2_C22 & !_LC4_C13 &  _LC4_C22;

-- Node name is '|clkdiv:5|:181' = '|clkdiv:5|clk_count15' 
-- Equation name is '_LC6_C13', type is buried 
_LC6_C13 = DFFE( _EQ044, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ044 =  _LC2_C17 & !_LC5_C13 &  _LC6_C13
         #  _LC2_C17 &  _LC5_C13 & !_LC6_C13;

-- Node name is '|clkdiv:5|:180' = '|clkdiv:5|clk_count16' 
-- Equation name is '_LC8_C13', type is buried 
_LC8_C13 = DFFE( _EQ045, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ045 =  _LC2_C17 & !_LC7_C13 &  _LC8_C13
         #  _LC2_C17 &  _LC7_C13 & !_LC8_C13;

-- Node name is '|clkdiv:5|:179' = '|clkdiv:5|clk_count17' 
-- Equation name is '_LC3_C13', type is buried 
_LC3_C13 = DFFE( _EQ046, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ046 =  _LC2_C17 &  _LC3_C13 & !_LC8_C13
         #  _LC2_C17 &  _LC3_C13 & !_LC7_C13
         #  _LC2_C17 & !_LC3_C13 &  _LC7_C13 &  _LC8_C13;

-- Node name is '|clkdiv:5|:178' = '|clkdiv:5|clk_count18' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = DFFE( _EQ047, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ047 =  _LC1_C16 & !_LC2_C13 &  _LC2_C17
         # !_LC1_C16 &  _LC2_C13 &  _LC2_C17;

-- Node name is '|clkdiv:5|:177' = '|clkdiv:5|clk_count19' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = DFFE( _EQ048, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ048 = !_LC1_C16 &  _LC2_C17 &  _LC5_C16
         # !_LC2_C13 &  _LC2_C17 &  _LC5_C16
         #  _LC1_C16 &  _LC2_C13 &  _LC2_C17 & !_LC5_C16;

-- Node name is '|clkdiv:5|:176' = '|clkdiv:5|clk_count20' 
-- Equation name is '_LC6_C17', type is buried 
_LC6_C17 = DFFE( _EQ049, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ049 =  _LC2_C17 & !_LC5_C17 &  _LC6_C17
         #  _LC2_C17 &  _LC5_C17 & !_LC6_C17;

-- Node name is '|clkdiv:5|:175' = '|clkdiv:5|clk_count21' 
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = DFFE( _EQ050, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ050 =  _LC2_C17 & !_LC3_C17 &  _LC4_C17
         #  _LC2_C17 &  _LC3_C17 & !_LC4_C17;

-- Node name is '|clkdiv:5|:174' = '|clkdiv:5|clk_count22' 
-- Equation name is '_LC8_C17', type is buried 
_LC8_C17 = DFFE( _EQ051, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ051 =  _LC2_C17 & !_LC4_C17 &  _LC8_C17
         #  _LC2_C17 & !_LC3_C17 &  _LC8_C17
         #  _LC2_C17 &  _LC3_C17 &  _LC4_C17 & !_LC8_C17;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C24', type is buried 
!_LC3_C24 = _LC3_C24~NOT;
_LC3_C24~NOT = LCELL( _EQ052);
  _EQ052 = !_LC4_C24
         # !_LC6_C24
         # !_LC7_C24;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C24', type is buried 
!_LC2_C24 = _LC2_C24~NOT;
_LC2_C24~NOT = LCELL( _EQ053);
  _EQ053 = !_LC8_C24
         # !_LC3_C24;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:151' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = LCELL( _EQ054);
  _EQ054 =  _LC1_C24 &  _LC2_C24 &  _LC5_C24 &  _LC6_C21;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ055);
  _EQ055 =  _LC5_C15 &  _LC5_C21;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:163' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ056);
  _EQ056 =  _LC5_C15 &  _LC5_C21 &  _LC7_C21 &  _LC8_C21;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C22', type is buried 
_LC6_C22 = LCELL( _EQ057);
  _EQ057 =  _LC1_C21 &  _LC3_C22 &  _LC5_C22;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:175' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ058);
  _EQ058 =  _LC1_C21 &  _LC3_C22 &  _LC5_C22 &  _LC7_C22;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ059);
  _EQ059 =  _LC2_C22 &  _LC4_C13 &  _LC4_C22;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:187' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C13', type is buried 
_LC7_C13 = LCELL( _EQ060);
  _EQ060 =  _LC2_C22 &  _LC4_C13 &  _LC4_C22 &  _LC6_C13;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ061);
  _EQ061 =  _LC3_C13 &  _LC7_C13 &  _LC8_C13;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C17', type is buried 
_LC5_C17 = LCELL( _EQ062);
  _EQ062 =  _LC1_C16 &  _LC2_C13 &  _LC5_C16;

-- Node name is '|clkdiv:5|lpm_add_sub:201|addcore:adder|:207' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = LCELL( _EQ063);
  _EQ063 =  _LC1_C16 &  _LC2_C13 &  _LC5_C16 &  _LC6_C17;

-- Node name is '|clkdiv:5|:12' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = LCELL( _EQ064);
  _EQ064 = !_LC8_C17
         #  _LC1_C17 & !_LC4_C17 & !_LC6_C17;

-- Node name is '|clkdiv:5|:27' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = LCELL( _EQ065);
  _EQ065 =  _LC1_C13 & !_LC3_C13
         # !_LC1_C16
         # !_LC5_C16;

-- Node name is '|clkdiv:5|~34~1' 
-- Equation name is '_LC1_C13', type is buried 
-- synthesized logic cell 
_LC1_C13 = LCELL( _EQ066);
  _EQ066 = !_LC4_C13 & !_LC6_C13 & !_LC8_C13
         #  _LC1_C22 & !_LC6_C13 & !_LC8_C13;

-- Node name is '|clkdiv:5|:54' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ067);
  _EQ067 = !_LC4_C22 & !_LC5_C22 & !_LC7_C22
         #  _LC4_C21 & !_LC4_C22 & !_LC7_C22;

-- Node name is '|clkdiv:5|:69' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ068);
  _EQ068 =  _LC3_C21 & !_LC3_C22
         # !_LC3_C22 & !_LC7_C21
         # !_LC3_C22 & !_LC8_C21;

-- Node name is '|clkdiv:5|:84' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = LCELL( _EQ069);
  _EQ069 =  _LC2_C21 & !_LC5_C15 & !_LC6_C21;

-- Node name is '|clkdiv:5|:97' 
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = LCELL( _EQ070);
  _EQ070 = !_LC1_C24
         # !_LC5_C24
         # !_LC2_C24;

-- Node name is '|clkdiv:5|:200' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = DFFE( _EQ071, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ071 =  _LC4_C17 &  _LC8_C17
         #  _LC6_C17 &  _LC8_C17
         # !_LC1_C17 &  _LC8_C17;

-- Node name is '|p7segment:8|:36' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ072);
  _EQ072 = !_LC1_B11 &  _LC1_B13 & !_LC1_B17 & !_LC1_B18;

-- Node name is '|p7segment:8|:60' 
-- Equation name is '_LC3_B3', type is buried 
_LC3_B3  = LCELL( _EQ073);
  _EQ073 =  _LC1_B11 & !_LC1_B13 & !_LC1_B17 & !_LC1_B18;

-- Node name is '|p7segment:8|:144' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ074);
  _EQ074 = !_LC1_B11 &  _LC1_B13 &  _LC1_B17 &  _LC1_B18;

-- Node name is '|p7segment:8|~156~1' 
-- Equation name is '_LC2_B9', type is buried 
-- synthesized logic cell 
_LC2_B9  = LCELL( _EQ075);
  _EQ075 =  _LC1_B11 &  _LC1_B17;

-- Node name is '|p7segment:8|~218~1' 
-- Equation name is '_LC1_B4', type is buried 
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ076);
  _EQ076 =  _LC1_B17
         # !_LC1_B11
         #  _LC1_B13 &  _LC1_B18
         # !_LC1_B13 & !_LC1_B18;

-- Node name is '|p7segment:8|~218~2' 
-- Equation name is '_LC5_B3', type is buried 
-- synthesized logic cell 
_LC5_B3  = LCELL( _EQ077);
  _EQ077 = !_LC1_B17
         # !_LC1_B11
         # !_LC1_B13 &  _LC1_B18;

-- Node name is '|p7segment:8|:218' 
-- Equation name is '_LC8_B4', type is buried 
!_LC8_B4 = _LC8_B4~NOT;
_LC8_B4~NOT = LCELL( _EQ078);
  _EQ078 =  _LC1_B4 & !_LC3_B4 &  _LC5_B3 & !_LC6_B4;

-- Node name is '|p7segment:8|~227~1' 
-- Equation name is '_LC4_B3', type is buried 
-- synthesized logic cell 
_LC4_B3  = LCELL( _EQ079);
  _EQ079 = !_LC1_B11 &  _LC1_B13 &  _LC1_B17 & !_LC1_B18
         # !_LC1_B11 & !_LC1_B13 &  _LC1_B17 &  _LC1_B18
         #  _LC1_B11 &  _LC1_B13 & !_LC1_B17 & !_LC1_B18
         #  _LC1_B11 & !_LC1_B13 & !_LC1_B17 &  _LC1_B18;

-- Node name is '|p7segment:8|~227~2' 
-- Equation name is '_LC7_B4', type is buried 
-- synthesized logic cell 
_LC7_B4  = LCELL( _EQ080);
  _EQ080 = !_LC1_B11 & !_LC1_B13 & !_LC1_B18
         # !_LC1_B11 &  _LC1_B17 & !_LC1_B18
         # !_LC1_B11 & !_LC1_B13 &  _LC1_B17
         #  _LC1_B11 &  _LC1_B13 & !_LC1_B17 & !_LC1_B18
         #  _LC1_B11 & !_LC1_B13 & !_LC1