📄 top2.rpt
字号:
- 7 - B 18 OR2 s 0 3 0 1 |scan:1|~130~4
- 1 - B 17 DFFE 0 5 0 16 |scan:1|:131
- 1 - B 11 DFFE 0 5 0 15 |scan:1|:132
- 1 - B 13 DFFE 0 5 0 15 |scan:1|:133
- 1 - B 18 DFFE 0 5 0 16 |scan:1|:134
- 5 - B 02 DFFE 0 4 1 0 |scan:1|:179
- 8 - B 01 DFFE 0 3 1 0 |scan:1|:180
- 1 - B 22 DFFE 0 3 1 0 |scan:1|:181
- 7 - B 24 DFFE 0 3 1 0 |scan:1|:182
- 5 - B 24 DFFE 0 3 1 0 |scan:1|:183
- 3 - B 24 DFFE 0 3 1 0 |scan:1|:184
- 6 - B 07 AND2 0 2 0 1 |time1:13|lpm_add_sub:582|addcore:adder|:55
- 2 - B 06 AND2 0 2 0 1 |time1:13|lpm_add_sub:583|addcore:adder|:55
- 7 - B 06 AND2 0 3 0 1 |time1:13|lpm_add_sub:583|addcore:adder|:59
- 5 - B 16 AND2 0 2 0 1 |time1:13|lpm_add_sub:584|addcore:adder|:55
- 2 - B 19 AND2 0 3 0 1 |time1:13|lpm_add_sub:585|addcore:adder|:59
- 6 - B 15 AND2 0 3 0 1 |time1:13|lpm_add_sub:586|addcore:adder|:59
- 4 - B 21 AND2 0 2 0 1 |time1:13|lpm_add_sub:587|addcore:adder|:55
- 7 - B 21 AND2 0 3 0 1 |time1:13|lpm_add_sub:587|addcore:adder|:59
- 1 - B 15 AND2 0 4 0 6 |time1:13|:28
- 1 - B 19 AND2 0 4 0 7 |time1:13|:34
- 1 - B 06 AND2 0 4 0 8 |time1:13|:57
- 8 - B 07 OR2 0 4 0 1 |time1:13|:80
- 5 - B 07 OR2 0 4 0 1 |time1:13|:81
- 4 - B 06 OR2 0 3 0 1 |time1:13|:82
- 2 - B 20 DFFE 1 1 0 1 |time1:13|started (|time1:13|:122)
- 7 - B 07 DFFE 0 4 0 3 |time1:13|sec7 (|time1:13|:125)
- 4 - B 07 DFFE 0 4 0 4 |time1:13|sec6 (|time1:13|:126)
- 1 - B 23 DFFE 0 4 0 5 |time1:13|sec5 (|time1:13|:127)
- 3 - B 07 DFFE 0 4 0 5 |time1:13|sec4 (|time1:13|:128)
- 6 - B 06 DFFE 0 4 0 2 |time1:13|sec3 (|time1:13|:129)
- 8 - B 06 DFFE 0 4 0 3 |time1:13|sec2 (|time1:13|:130)
- 5 - B 06 DFFE 0 4 0 4 |time1:13|sec1 (|time1:13|:131)
- 3 - B 06 DFFE 0 2 0 5 |time1:13|sec0 (|time1:13|:132)
- 6 - B 19 AND2 s 0 2 0 1 |time1:13|~161~1
- 2 - B 14 AND2 0 2 0 6 |time1:13|:161
- 1 - B 16 AND2 0 4 0 8 |time1:13|:162
- 2 - B 07 AND2 s ! 0 3 0 1 |time1:13|~179~1
- 1 - B 07 AND2 0 3 0 13 |time1:13|:179
- 6 - B 16 OR2 0 4 0 1 |time1:13|:201
- 4 - B 16 OR2 0 4 0 1 |time1:13|:202
- 6 - B 23 OR2 0 3 0 1 |time1:13|:203
- 3 - B 19 OR2 0 4 0 1 |time1:13|:255
- 8 - B 14 OR2 0 3 0 1 |time1:13|:258
- 4 - B 23 OR2 0 3 0 1 |time1:13|:262
- 7 - B 14 AND2 s ! 0 3 0 1 |time1:13|~314~1
- 7 - B 19 OR2 s 0 4 0 1 |time1:13|~315~1
- 1 - B 14 AND2 s ! 0 2 0 12 |time1:13|~317~1
- 5 - B 19 DFFE 0 4 0 3 |time1:13|min7 (|time1:13|:322)
- 3 - B 14 DFFE 0 4 0 3 |time1:13|min6 (|time1:13|:323)
- 4 - B 19 DFFE 0 5 0 5 |time1:13|min5 (|time1:13|:324)
- 6 - B 14 DFFE 0 5 0 6 |time1:13|min4 (|time1:13|:325)
- 7 - B 16 DFFE 0 5 0 3 |time1:13|min3 (|time1:13|:326)
- 2 - B 16 DFFE 0 5 0 4 |time1:13|min2 (|time1:13|:327)
- 5 - B 23 DFFE 0 5 0 5 |time1:13|min1 (|time1:13|:328)
- 2 - B 23 DFFE 0 4 0 6 |time1:13|min0 (|time1:13|:329)
- 8 - B 19 AND2 s 0 2 0 1 |time1:13|~370~1
- 7 - B 15 OR2 0 4 0 1 |time1:13|:417
- 5 - B 14 OR2 0 3 0 1 |time1:13|:420
- 5 - B 15 AND2 s ! 0 3 0 1 |time1:13|~468~1
- 3 - B 21 AND2 s ! 0 2 0 3 |time1:13|~475~1
- 8 - B 15 OR2 s 0 3 0 1 |time1:13|~477~1
- 5 - B 21 DFFE 0 4 0 1 |time1:13|hour7 (|time1:13|:480)
- 1 - B 21 DFFE 0 4 0 2 |time1:13|hour6 (|time1:13|:481)
- 2 - B 21 DFFE 0 4 0 3 |time1:13|hour5 (|time1:13|:482)
- 8 - B 21 DFFE 0 4 0 4 |time1:13|hour4 (|time1:13|:483)
- 4 - B 15 DFFE 0 5 0 3 |time1:13|hour3 (|time1:13|:484)
- 2 - B 15 DFFE 0 4 0 3 |time1:13|hour2 (|time1:13|:485)
- 3 - B 15 DFFE 0 5 0 5 |time1:13|hour1 (|time1:13|:486)
- 4 - B 14 DFFE 0 5 0 6 |time1:13|hour0 (|time1:13|:487)
- 5 - B 20 AND2 ! 1 1 0 48 |time1:13|:489
- 4 - B 17 DFFE 0 3 0 1 |time1:13|:505
- 4 - B 11 DFFE 0 3 0 1 |time1:13|:506
- 4 - B 13 DFFE 0 3 0 1 |time1:13|:507
- 6 - B 21 DFFE 0 3 0 1 |time1:13|:508
- 3 - B 17 DFFE 0 3 0 1 |time1:13|:518
- 3 - B 11 DFFE 0 3 0 1 |time1:13|:519
- 3 - B 13 DFFE 0 3 0 1 |time1:13|:520
- 3 - B 18 DFFE 0 3 0 1 |time1:13|:521
- 2 - B 17 DFFE 0 3 0 1 |time1:13|:531
- 2 - B 11 DFFE 0 3 0 1 |time1:13|:532
- 2 - B 13 DFFE 0 3 0 1 |time1:13|:533
- 2 - B 18 DFFE 0 3 0 1 |time1:13|:534
- 3 - B 16 DFFE 0 3 0 1 |time1:13|:544
- 7 - B 08 DFFE 0 3 0 1 |time1:13|:545
- 4 - B 20 DFFE 0 3 0 1 |time1:13|:546
- 8 - B 23 DFFE 0 3 0 1 |time1:13|:547
- 1 - B 05 DFFE 0 3 0 1 |time1:13|:557
- 6 - B 08 DFFE 0 3 0 1 |time1:13|:558
- 3 - B 20 DFFE 0 3 0 1 |time1:13|:559
- 7 - B 23 DFFE 0 3 0 1 |time1:13|:560
- 7 - B 17 DFFE 0 3 0 1 |time1:13|:570
- 7 - B 11 DFFE 0 3 0 1 |time1:13|:571
- 7 - B 13 DFFE 0 3 0 1 |time1:13|:572
- 6 - B 18 DFFE 0 3 0 1 |time1:13|:573
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\top2.rpt
top2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 14/ 48( 29%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 28/ 96( 29%) 22/ 48( 45%) 20/ 48( 41%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 19/ 48( 39%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\top2.rpt
top2
** CLOCK SIGNALS **
Type Fan-out Name
DFF 49 |clkdiv:5|:200
INPUT 40 clk
DFF 13 |clkdiv2:11|:136
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\top2.rpt
top2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 49 reset
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\top2.rpt
top2
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC4_B12;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC1_B10;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC1_B9;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC7_B9;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC8_B10;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC2_B4;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC4_B4;
-- Node name is 'en1'
-- Equation name is 'en1', type is output
en1 = _LC3_B24;
-- Node name is 'en2'
-- Equation name is 'en2', type is output
en2 = _LC5_B24;
-- Node name is 'en3'
-- Equation name is 'en3', type is output
en3 = _LC7_B24;
-- Node name is 'en4'
-- Equation name is 'en4', type is output
en4 = _LC1_B22;
-- Node name is 'en5'
-- Equation name is 'en5', type is output
en5 = _LC8_B1;
-- Node name is 'en6'
-- Equation name is 'en6', type is output
en6 = _LC5_B2;
-- Node name is '|clkdiv2:11|:132' = '|clkdiv2:11|clk_count0'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC1_A12 & !_LC4_A6;
-- Node name is '|clkdiv2:11|:131' = '|clkdiv2:11|clk_count1'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC1_A12 & _LC4_A6 & !_LC5_A6
# _LC1_A12 & !_LC4_A6 & _LC5_A6;
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