scan.v

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

module scan(clk,data,en,reg1,reg2,reg3,reg4,reg5,reg6);
  input clk;
  output[3:0] data;
  output[6:1] en;
  input[3:0] reg1,reg2,reg3,reg4,reg5,reg6;
  reg[3:0] data;
  reg[6:1] en;
  
 // reg[3:0] reg1,reg2,reg3,reg4,reg5,reg6;
  reg[2:0] state;
  parameter
    s1=3'b001,
    s2=3'b010,
    s3=3'b011,
    s4=3'b100,
    s5=3'b101,
    s6=3'b110;
  
  always @(posedge clk)
    begin
       case(state)
         s1:begin state<=s2;data<=reg1;en<=1;end
         s2:begin state<=s3;data<=reg2;en<=2;end
         s3:begin state<=s4;data<=reg3;en<=4;end
         s4:begin state<=s5;data<=reg4;en<=8;end
         s5:begin state<=s6;data<=reg5;en<=16;end
         s6:begin state<=s1;data<=reg6;en<=32;end
         default:state<=s1;
       endcase
    end
endmodule