clkscan3_top.rpt

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Project Informatione:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/29/2003 17:31:36

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

clkscan3_top
      EPF10K10LC84-3       3      13     0    0         0  %    194      33 %

User Pins:                 3      13     0  



Project Informatione:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

clkscan3_top@1                    clk
clkscan3_top@23                   out0
clkscan3_top@22                   out1
clkscan3_top@21                   out2
clkscan3_top@19                   out3
clkscan3_top@18                   out4
clkscan3_top@17                   out5
clkscan3_top@16                   out6
clkscan3_top@84                   reset
clkscan3_top@78                   scan_en1
clkscan3_top@79                   scan_en2
clkscan3_top@80                   scan_en3
clkscan3_top@81                   scan_en4
clkscan3_top@10                   scan_en5
clkscan3_top@11                   scan_en6
clkscan3_top@44                   start


Project Informatione:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt

** FILE HIERARCHY **



|clkdiv:5|
|clkdiv:5|lpm_add_sub:201|
|clkdiv:5|lpm_add_sub:201|addcore:adder|
|clkdiv:5|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|clkdiv:5|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|clkdiv:5|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|p7segment:8|
|clkdiv2:11|
|clkdiv2:11|lpm_add_sub:137|
|clkdiv2:11|lpm_add_sub:137|addcore:adder|
|clkdiv2:11|lpm_add_sub:137|altshift:result_ext_latency_ffs|
|clkdiv2:11|lpm_add_sub:137|altshift:carry_ext_latency_ffs|
|clkdiv2:11|lpm_add_sub:137|altshift:oflow_ext_latency_ffs|
|timer:15|
|timer:15|lpm_add_sub:299|
|timer:15|lpm_add_sub:299|addcore:adder|
|timer:15|lpm_add_sub:299|altshift:result_ext_latency_ffs|
|timer:15|lpm_add_sub:299|altshift:carry_ext_latency_ffs|
|timer:15|lpm_add_sub:299|altshift:oflow_ext_latency_ffs|
|timer:15|lpm_add_sub:300|
|timer:15|lpm_add_sub:300|addcore:adder|
|timer:15|lpm_add_sub:300|altshift:result_ext_latency_ffs|
|timer:15|lpm_add_sub:300|altshift:carry_ext_latency_ffs|
|timer:15|lpm_add_sub:300|altshift:oflow_ext_latency_ffs|
|timer:15|lpm_add_sub:301|
|timer:15|lpm_add_sub:301|addcore:adder|
|timer:15|lpm_add_sub:301|altshift:result_ext_latency_ffs|
|timer:15|lpm_add_sub:301|altshift:carry_ext_latency_ffs|
|timer:15|lpm_add_sub:301|altshift:oflow_ext_latency_ffs|
|timer:15|lpm_add_sub:302|
|timer:15|lpm_add_sub:302|addcore:adder|
|timer:15|lpm_add_sub:302|altshift:result_ext_latency_ffs|
|timer:15|lpm_add_sub:302|altshift:carry_ext_latency_ffs|
|timer:15|lpm_add_sub:302|altshift:oflow_ext_latency_ffs|
|timer:15|lpm_add_sub:303|
|timer:15|lpm_add_sub:303|addcore:adder|
|timer:15|lpm_add_sub:303|altshift:result_ext_latency_ffs|
|timer:15|lpm_add_sub:303|altshift:carry_ext_latency_ffs|
|timer:15|lpm_add_sub:303|altshift:oflow_ext_latency_ffs|
|timer:15|lpm_add_sub:304|
|timer:15|lpm_add_sub:304|addcore:adder|
|timer:15|lpm_add_sub:304|altshift:result_ext_latency_ffs|
|timer:15|lpm_add_sub:304|altshift:carry_ext_latency_ffs|
|timer:15|lpm_add_sub:304|altshift:oflow_ext_latency_ffs|
|clkscan3:16|
|clkscan3:16|lpm_add_sub:298|
|clkscan3:16|lpm_add_sub:298|addcore:adder|
|clkscan3:16|lpm_add_sub:298|altshift:result_ext_latency_ffs|
|clkscan3:16|lpm_add_sub:298|altshift:carry_ext_latency_ffs|
|clkscan3:16|lpm_add_sub:298|altshift:oflow_ext_latency_ffs|


Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top

***** Logic for device 'clkscan3_top' compiled without errors.




Device: EPF10K10LC84-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                         ^     
                                                                         C     
                s  s  R  R  R  R  R     R           R     s  s  s  s     O     
                c  c  E  E  E  E  E     E           E     c  c  c  c     N     
                a  a  S  S  S  S  S  V  S  G        S  G  a  a  a  a     F     
                n  n  E  E  E  E  E  C  E  N     r  E  N  n  n  n  n     _  ^  
                _  _  R  R  R  R  R  C  R  D     e  R  D  _  _  _  _  #  D  n  
                e  e  V  V  V  V  V  I  V  I  c  s  V  I  e  e  e  e  T  O  C  
                n  n  E  E  E  E  E  N  E  N  l  e  E  N  n  n  n  n  C  N  E  
                6  5  D  D  D  D  D  T  D  T  k  t  D  T  4  3  2  1  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | RESERVED 
      ^nCE | 14                                                              72 | RESERVED 
      #TDI | 15                                                              71 | RESERVED 
      out6 | 16                                                              70 | RESERVED 
      out5 | 17                                                              69 | RESERVED 
      out4 | 18                                                              68 | GNDINT 
      out3 | 19                                                              67 | RESERVED 
    VCCINT | 20                                                              66 | RESERVED 
      out2 | 21                                                              65 | RESERVED 
      out1 | 22                        EPF10K10LC84-3                        64 | RESERVED 
      out0 | 23                                                              63 | VCCINT 
  RESERVED | 24                                                              62 | RESERVED 
  RESERVED | 25                                                              61 | RESERVED 
    GNDINT | 26                                                              60 | RESERVED 
  RESERVED | 27                                                              59 | RESERVED 
  RESERVED | 28                                                              58 | RESERVED 
  RESERVED | 29                                                              57 | #TMS 
  RESERVED | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | RESERVED 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  R  R  R  R  R  V  G  G  G  s  V  G  R  R  R  R  R  R  R  
                C  n  E  E  E  E  E  C  N  N  N  t  C  N  E  E  E  E  E  E  E  
                C  C  S  S  S  S  S  C  D  D  D  a  C  D  S  S  S  S  S  S  S  
                I  O  E  E  E  E  E  I  I  I  I  r  I  I  E  E  E  E  E  E  E  
                N  N  R  R  R  R  R  N  N  N  N  t  N  N  R  R  R  R  R  R  R  
                T  F  V  V  V  V  V  T  T  T  T     T  T  V  V  V  V  V  V  V  
                   I  E  E  E  E  E                       E  E  E  E  E  E  E  
                   G  D  D  D  D  D                       D  D  D  D  D  D  D  
                                                                               
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       1/22(  4%)   
A3       2/ 8( 25%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2       2/22(  9%)   
A4       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       7/22( 31%)   
A5       7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2       6/22( 27%)   
A8       2/ 8( 25%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       4/22( 18%)   
A10      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2       4/22( 18%)   
A11      8/ 8(100%)   0/ 8(  0%)   7/ 8( 87%)    1/2    0/2       3/22( 13%)   
B1       7/ 8( 87%)   2/ 8( 25%)   1/ 8( 12%)    1/2    0/2      13/22( 59%)   
B2       8/ 8(100%)   1/ 8( 12%)   6/ 8( 75%)    0/2    0/2       5/22( 22%)   
B3       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       5/22( 22%)   
B5       8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    1/2       3/22( 13%)   
B7       8/ 8(100%)   3/ 8( 37%)   3/ 8( 37%)    0/2    0/2      10/22( 45%)   
B8       8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    1/2       5/22( 22%)   
B11      3/ 8( 37%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       5/22( 22%)   
B12      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    1/2    2/2       2/22(  9%)   
B13      8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       7/22( 31%)   
B14      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    1/2       7/22( 31%)   
B15      6/ 8( 75%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2      16/22( 72%)   
B16      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       1/22(  4%)   
B17      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       4/22( 18%)   
B18      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    1/2       2/22(  9%)   
B19      8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2      14/22( 63%)   
B20      5/ 8( 62%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2      13/22( 59%)   
B21      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
B22      8/ 8(100%)   1/ 8( 12%)   7/ 8( 87%)    1/2    0/2       2/22(  9%)   
B23      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       5/22( 22%)   
B24      3/ 8( 37%)   3/ 8( 37%)   0/ 8(  0%)    1/2    0/2       5/22( 22%)   
C2       6/ 8( 75%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       3/22( 13%)   
C5       6/ 8( 75%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       1/22(  4%)   
C6       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       5/22( 22%)   
C8       8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    1/2    0/2       3/22( 13%)   


Embedded             Column       Row