scan.rpt

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

         #  _LC7_A16 & !state0 & !state1 & !state2;

-- Node name is ':127' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ014);
  _EQ014 =  _LC3_A17 &  state0 &  state1 &  state2
         #  _LC3_A17 & !state0 & !state1 & !state2;

-- Node name is '~128~1' 
-- Equation name is '~128~1', location is LC2_A20, type is buried.
-- synthesized logic cell 
_LC2_A20 = LCELL( _EQ015);
  _EQ015 =  _LC2_A15 &  reg53
         #  _LC8_A16 &  reg43;

-- Node name is '~128~2' 
-- Equation name is '~128~2', location is LC4_A20, type is buried.
-- synthesized logic cell 
_LC4_A20 = LCELL( _EQ016);
  _EQ016 =  _LC8_A20 &  reg63
         #  _LC2_A20;

-- Node name is '~128~3' 
-- Equation name is '~128~3', location is LC6_A20, type is buried.
-- synthesized logic cell 
_LC6_A20 = LCELL( _EQ017);
  _EQ017 =  _LC4_A15 &  reg23
         #  _LC3_A20 &  reg13;

-- Node name is '~128~4' 
-- Equation name is '~128~4', location is LC7_A20, type is buried.
-- synthesized logic cell 
_LC7_A20 = LCELL( _EQ018);
  _EQ018 =  _LC1_A16 &  reg33
         #  _LC6_A20;

-- Node name is '~129~1' 
-- Equation name is '~129~1', location is LC5_A15, type is buried.
-- synthesized logic cell 
_LC5_A15 = LCELL( _EQ019);
  _EQ019 =  _LC2_A15 &  reg52
         #  _LC8_A16 &  reg42;

-- Node name is '~129~2' 
-- Equation name is '~129~2', location is LC6_A15, type is buried.
-- synthesized logic cell 
_LC6_A15 = LCELL( _EQ020);
  _EQ020 =  _LC8_A20 &  reg62
         #  _LC5_A15;

-- Node name is '~129~3' 
-- Equation name is '~129~3', location is LC7_A15, type is buried.
-- synthesized logic cell 
_LC7_A15 = LCELL( _EQ021);
  _EQ021 =  _LC4_A15 &  reg22
         #  _LC3_A20 &  reg12;

-- Node name is '~129~4' 
-- Equation name is '~129~4', location is LC8_A15, type is buried.
-- synthesized logic cell 
_LC8_A15 = LCELL( _EQ022);
  _EQ022 =  _LC1_A16 &  reg32
         #  _LC7_A15;

-- Node name is '~130~1' 
-- Equation name is '~130~1', location is LC3_A16, type is buried.
-- synthesized logic cell 
_LC3_A16 = LCELL( _EQ023);
  _EQ023 =  _LC2_A15 &  reg51
         #  _LC8_A16 &  reg41;

-- Node name is '~130~2' 
-- Equation name is '~130~2', location is LC6_A16, type is buried.
-- synthesized logic cell 
_LC6_A16 = LCELL( _EQ024);
  _EQ024 =  _LC8_A20 &  reg61
         #  _LC3_A16;

-- Node name is '~130~3' 
-- Equation name is '~130~3', location is LC7_A18, type is buried.
-- synthesized logic cell 
_LC7_A18 = LCELL( _EQ025);
  _EQ025 =  _LC4_A15 &  reg21
         #  _LC3_A20 &  reg11;

-- Node name is '~130~4' 
-- Equation name is '~130~4', location is LC5_A18, type is buried.
-- synthesized logic cell 
_LC5_A18 = LCELL( _EQ026);
  _EQ026 =  _LC1_A16 &  reg31
         #  _LC7_A18;

-- Node name is '~131~1' 
-- Equation name is '~131~1', location is LC4_A17, type is buried.
-- synthesized logic cell 
_LC4_A17 = LCELL( _EQ027);
  _EQ027 =  _LC2_A15 &  reg50
         #  _LC8_A16 &  reg40;

-- Node name is '~131~2' 
-- Equation name is '~131~2', location is LC5_A17, type is buried.
-- synthesized logic cell 
_LC5_A17 = LCELL( _EQ028);
  _EQ028 =  _LC8_A20 &  reg60
         #  _LC4_A17;

-- Node name is '~131~3' 
-- Equation name is '~131~3', location is LC7_A17, type is buried.
-- synthesized logic cell 
_LC7_A17 = LCELL( _EQ029);
  _EQ029 =  _LC4_A15 &  reg20
         #  _LC3_A20 &  reg10;

-- Node name is '~131~4' 
-- Equation name is '~131~4', location is LC8_A17, type is buried.
-- synthesized logic cell 
_LC8_A17 = LCELL( _EQ030);
  _EQ030 =  _LC1_A16 &  reg30
         #  _LC7_A17;

-- Node name is ':132' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = DFFE( _EQ031, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ031 =  _LC1_A20
         #  _LC4_A20
         #  _LC7_A20;

-- Node name is ':133' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = DFFE( _EQ032, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ032 =  _LC1_A15
         #  _LC6_A15
         #  _LC8_A15;

-- Node name is ':134' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = DFFE( _EQ033, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ033 =  _LC2_A16
         #  _LC6_A16
         #  _LC5_A18;

-- Node name is ':135' 
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = DFFE( _EQ034, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ034 =  _LC1_A17
         #  _LC5_A17
         #  _LC8_A17;

-- Node name is ':184' 
-- Equation name is '_LC3_A18', type is buried 
_LC3_A18 = DFFE( _EQ035, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ035 =  _LC3_A18 & !_LC5_A16
         #  _LC8_A20;

-- Node name is ':185' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = DFFE( _EQ036, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ036 =  _LC1_A18 & !_LC5_A16
         #  _LC2_A15;

-- Node name is ':186' 
-- Equation name is '_LC4_A18', type is buried 
_LC4_A18 = DFFE( _EQ037, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ037 =  _LC4_A18 & !_LC5_A16
         #  _LC8_A16;

-- Node name is ':187' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = DFFE( _EQ038, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ038 =  _LC2_A18 & !_LC5_A16
         #  _LC1_A16;

-- Node name is ':188' 
-- Equation name is '_LC8_A18', type is buried 
_LC8_A18 = DFFE( _EQ039, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ039 = !_LC5_A16 &  _LC8_A18
         #  _LC4_A15;

-- Node name is ':189' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = DFFE( _EQ040, GLOBAL( clk),  VCC,  VCC, !_LC1_A13);
  _EQ040 = !_LC5_A16 &  _LC6_A18
         #  _LC3_A20;



Project Information                   f:\verilog hdl\clkscan\clkscan3\scan.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 33,192K