📄 scan.rpt
字号:
- 1 - A 16 AND2 0 3 0 6 :51
- 8 - A 16 OR2 ! 0 3 0 7 :58
- 2 - A 15 AND2 0 3 0 7 :65
- 8 - A 20 OR2 ! 0 3 0 6 :72
- 5 - A 16 OR2 0 3 0 9 :83
- 4 - A 16 DFFE + 0 4 0 11 state2 (:91)
- 2 - A 17 DFFE + 0 4 0 11 state1 (:92)
- 6 - A 17 DFFE + ! 0 4 0 11 state0 (:93)
- 1 - A 20 OR2 0 4 0 1 :124
- 1 - A 15 OR2 0 4 0 1 :125
- 2 - A 16 OR2 0 4 0 1 :126
- 1 - A 17 OR2 0 4 0 1 :127
- 2 - A 20 OR2 s 2 2 0 1 ~128~1
- 4 - A 20 OR2 s 1 2 0 1 ~128~2
- 6 - A 20 OR2 s 2 2 0 1 ~128~3
- 7 - A 20 OR2 s 1 2 0 1 ~128~4
- 5 - A 15 OR2 s 2 2 0 1 ~129~1
- 6 - A 15 OR2 s 1 2 0 1 ~129~2
- 7 - A 15 OR2 s 2 2 0 1 ~129~3
- 8 - A 15 OR2 s 1 2 0 1 ~129~4
- 3 - A 16 OR2 s 2 2 0 1 ~130~1
- 6 - A 16 OR2 s 1 2 0 1 ~130~2
- 7 - A 18 OR2 s 2 2 0 1 ~130~3
- 5 - A 18 OR2 s 1 2 0 1 ~130~4
- 4 - A 17 OR2 s 2 2 0 1 ~131~1
- 5 - A 17 OR2 s 1 2 0 1 ~131~2
- 7 - A 17 OR2 s 2 2 0 1 ~131~3
- 8 - A 17 OR2 s 1 2 0 1 ~131~4
- 5 - A 20 DFFE + 0 4 1 1 :132
- 3 - A 15 DFFE + 0 4 1 1 :133
- 7 - A 16 DFFE + 0 4 1 1 :134
- 3 - A 17 DFFE + 0 4 1 1 :135
- 3 - A 18 DFFE + 0 3 1 0 :184
- 1 - A 18 DFFE + 0 3 1 0 :185
- 4 - A 18 DFFE + 0 3 1 0 :186
- 2 - A 18 DFFE + 0 3 1 0 :187
- 8 - A 18 DFFE + 0 3 1 0 :188
- 6 - A 18 DFFE + 0 3 1 0 :189
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\scan.rpt
scan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 18/ 96( 18%) 0/ 48( 0%) 21/ 48( 43%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\scan.rpt
scan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\scan.rpt
scan
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 start
Device-Specific Information: f:\verilog hdl\clkscan\clkscan3\scan.rpt
scan
** EQUATIONS **
clk : INPUT;
reg10 : INPUT;
reg11 : INPUT;
reg12 : INPUT;
reg13 : INPUT;
reg20 : INPUT;
reg21 : INPUT;
reg22 : INPUT;
reg23 : INPUT;
reg30 : INPUT;
reg31 : INPUT;
reg32 : INPUT;
reg33 : INPUT;
reg40 : INPUT;
reg41 : INPUT;
reg42 : INPUT;
reg43 : INPUT;
reg50 : INPUT;
reg51 : INPUT;
reg52 : INPUT;
reg53 : INPUT;
reg60 : INPUT;
reg61 : INPUT;
reg62 : INPUT;
reg63 : INPUT;
start : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC3_A17;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC7_A16;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC3_A15;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC5_A20;
-- Node name is 'en1'
-- Equation name is 'en1', type is output
en1 = _LC6_A18;
-- Node name is 'en2'
-- Equation name is 'en2', type is output
en2 = _LC8_A18;
-- Node name is 'en3'
-- Equation name is 'en3', type is output
en3 = _LC2_A18;
-- Node name is 'en4'
-- Equation name is 'en4', type is output
en4 = _LC4_A18;
-- Node name is 'en5'
-- Equation name is 'en5', type is output
en5 = _LC1_A18;
-- Node name is 'en6'
-- Equation name is 'en6', type is output
en6 = _LC3_A18;
-- Node name is 'start~1'
-- Equation name is 'start~1', location is LC1_A13, type is buried.
-- synthesized logic cell
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL(!start);
-- Node name is ':93' = 'state0'
-- Equation name is 'state0', location is LC6_A17, type is buried.
!state0 = state0~NOT;
state0~NOT = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ001 = !_LC4_A15 & _LC5_A16 & !_LC8_A16 & !_LC8_A20;
-- Node name is ':92' = 'state1'
-- Equation name is 'state1', location is LC2_A17, type is buried.
state1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ002 = _LC2_A15
# _LC3_A20
# _LC4_A15
# !_LC5_A16;
-- Node name is ':91' = 'state2'
-- Equation name is 'state2', location is LC4_A16, type is buried.
state2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ003 = !_LC5_A16
# _LC8_A16
# _LC1_A16
# _LC2_A15;
-- Node name is ':37'
-- Equation name is '_LC3_A20', type is buried
_LC3_A20 = LCELL( _EQ004);
_EQ004 = state0 & !state1 & !state2;
-- Node name is ':44'
-- Equation name is '_LC4_A15', type is buried
!_LC4_A15 = _LC4_A15~NOT;
_LC4_A15~NOT = LCELL( _EQ005);
_EQ005 = state2
# !state1
# state0;
-- Node name is ':51'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ006);
_EQ006 = state0 & state1 & !state2;
-- Node name is ':58'
-- Equation name is '_LC8_A16', type is buried
!_LC8_A16 = _LC8_A16~NOT;
_LC8_A16~NOT = LCELL( _EQ007);
_EQ007 = !state2
# state1
# state0;
-- Node name is ':65'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ008);
_EQ008 = state0 & !state1 & state2;
-- Node name is ':72'
-- Equation name is '_LC8_A20', type is buried
!_LC8_A20 = _LC8_A20~NOT;
_LC8_A20~NOT = LCELL( _EQ009);
_EQ009 = !state2
# !state1
# state0;
-- Node name is ':83'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ010);
_EQ010 = state0 & !state1
# state1 & !state2
# state0 & !state2
# !state1 & state2
# !state0 & state1;
-- Node name is ':124'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ011);
_EQ011 = _LC5_A20 & state0 & state1 & state2
# _LC5_A20 & !state0 & !state1 & !state2;
-- Node name is ':125'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ012);
_EQ012 = _LC3_A15 & state0 & state1 & state2
# _LC3_A15 & !state0 & !state1 & !state2;
-- Node name is ':126'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ013);
_EQ013 = _LC7_A16 & state0 & state1 & state2
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