clkscan3_old.v

来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· Verilog 代码 · 共 34 行

module clkscan3_old(clk,sec,min,hour,scan_data,scan_en);
  input clk;
  input[7:0] sec,min,hour; // 秒、分、时输入信号
  output[3:0] scan_data;
  output[6:1] scan_en;     // 分别驱动各数码管共阴极引脚SC6~SC1
  reg[3:0] scan_data;
  reg[6:1] scan_en;  
  
  reg[2:0] state;    // 状态机，s5~s1为state的6个状态，分别用于控制scan_en[6:1]
  parameter
    s1=3'b001,
    s2=3'b010,
    s3=3'b011,
    s4=3'b100,
    s5=3'b101,
    s6=3'b110;
  
  always @(posedge clk)
    begin
       case(state)
         s1:begin state<=s2;scan_data<=hour[7:4];scan_en<=1;end // 在S1状态下,DP1亮,显示小时高位
         s2:begin state<=s3;scan_data<=hour[3:0];scan_en<=2;end
         s3:begin state<=s4;scan_data<=min[7:4];scan_en<=4;end
         s4:begin state<=s5;scan_data<=min[3:0];scan_en<=8;end
         s5:begin state<=s6;scan_data<=sec[7:4];scan_en<=16;end
         s6:begin state<=s1;scan_data<=sec[3:0];scan_en<=32;end
         default:state<=s1;
       endcase
    end
endmodule

// 此程序与clkscan3.v类似，只是这里采用的是非阻塞赋值语句，
// scan_en和scan_data都比state的状态滞后了一个时钟周期