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📄 time1.rpt

📁 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块
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         #  _LC4_C6;

-- Node name is ':578' 
-- Equation name is '_LC7_C11', type is buried 
_LC7_C11 = LCELL( _EQ091);
  _EQ091 =  _LC1_C20 &  _LC6_C11
         #  hour6 & !_LC1_C20 & !reset;

-- Node name is ':579' 
-- Equation name is '_LC8_C9', type is buried 
_LC8_C9  = LCELL( _EQ092);
  _EQ092 =  _LC1_C20 &  _LC7_C9
         #  hour5 & !_LC1_C20 & !reset;

-- Node name is ':582' 
-- Equation name is '_LC6_C8', type is buried 
_LC6_C8  = LCELL( _EQ093);
  _EQ093 =  _LC1_C20 &  _LC4_C8
         #  hour2 & !_LC1_C20 & !reset;

-- Node name is ':583' 
-- Equation name is '_LC8_C6', type is buried 
_LC8_C6  = LCELL( _EQ094);
  _EQ094 =  _LC1_C20 &  _LC5_C6
         #  hour1 & !_LC1_C20 & !reset;

-- Node name is '~602~1' 
-- Equation name is '~602~1', location is LC3_C11, type is buried.
-- synthesized logic cell 
_LC3_C11 = LCELL( _EQ095);
  _EQ095 = !hour5
         # !hour4
         # !hour6;

-- Node name is '~605~1' 
-- Equation name is '~605~1', location is LC5_C5, type is buried.
-- synthesized logic cell 
_LC5_C5  = LCELL( _EQ096);
  _EQ096 = !_LC3_C6 & !reset
         # !_LC8_C14 & !reset
         #  _LC8_C5 & !reset;

-- Node name is '~606~1' 
-- Equation name is '~606~1', location is LC7_C8, type is buried.
-- synthesized logic cell 
_LC7_C8  = LCELL( _EQ097);
  _EQ097 =  hour0 &  hour1 &  hour2 & !hour3
         # !hour1 &  hour3
         # !hour0 &  hour3
         # !hour2 &  hour3;

-- Node name is '~606~2' 
-- Equation name is '~606~2', location is LC8_C8, type is buried.
-- synthesized logic cell 
_LC8_C8  = LCELL( _EQ098);
  _EQ098 =  _LC3_C6 &  _LC7_C8 &  _LC8_C5;

-- Node name is '~609~1' 
-- Equation name is '~609~1', location is LC7_C6, type is buried.
-- synthesized logic cell 
_LC7_C6  = LCELL( _EQ099);
  _EQ099 = !_LC3_C6
         # !_LC8_C14;

-- Node name is ':631' 
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = DFFE( _EQ100, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ100 =  hour7 &  started
         #  _LC1_C5 & !reset & !started;

-- Node name is ':632' 
-- Equation name is '_LC8_C21', type is buried 
_LC8_C21 = DFFE( _EQ101, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ101 =  hour6 &  started
         #  _LC8_C21 & !reset & !started;

-- Node name is ':633' 
-- Equation name is '_LC3_C9', type is buried 
_LC3_C9  = DFFE( _EQ102, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ102 =  hour5 &  started
         #  _LC3_C9 & !reset & !started;

-- Node name is ':634' 
-- Equation name is '_LC5_C9', type is buried 
_LC5_C9  = DFFE( _EQ103, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ103 =  hour4 &  started
         #  _LC5_C9 & !reset & !started;

-- Node name is ':659' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = DFFE( _EQ104, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ104 =  hour3 &  started
         #  _LC5_C21 & !reset & !started;

-- Node name is ':660' 
-- Equation name is '_LC6_C9', type is buried 
_LC6_C9  = DFFE( _EQ105, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ105 =  hour2 &  started
         #  _LC6_C9 & !reset & !started;

-- Node name is ':661' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = DFFE( _EQ106, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ106 =  hour1 &  started
         #  _LC1_C14 & !reset & !started;

-- Node name is ':662' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = DFFE( _EQ107, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ107 =  hour0 &  started
         #  _LC4_C21 & !reset & !started;

-- Node name is ':687' 
-- Equation name is '_LC8_C20', type is buried 
_LC8_C20 = DFFE( _EQ108, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ108 =  min7 &  started
         #  _LC8_C20 & !reset & !started;

-- Node name is ':688' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = DFFE( _EQ109, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ109 =  min6 &  started
         #  _LC1_C12 & !reset & !started;

-- Node name is ':689' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = DFFE( _EQ110, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ110 =  min5 &  started
         #  _LC7_C21 & !reset & !started;

-- Node name is ':690' 
-- Equation name is '_LC8_C17', type is buried 
_LC8_C17 = DFFE( _EQ111, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ111 =  min4 &  started
         #  _LC8_C17 & !reset & !started;

-- Node name is ':715' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = DFFE( _EQ112, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ112 =  min3 &  started
         #  _LC6_C12 & !reset & !started;

-- Node name is ':716' 
-- Equation name is '_LC2_C24', type is buried 
_LC2_C24 = DFFE( _EQ113, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ113 =  min2 &  started
         #  _LC2_C24 & !reset & !started;

-- Node name is ':717' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = DFFE( _EQ114, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ114 =  min1 &  started
         #  _LC3_C21 & !reset & !started;

-- Node name is ':718' 
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = DFFE( _EQ115, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ115 =  min0 &  started
         #  _LC2_C21 & !reset & !started;

-- Node name is ':743' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = DFFE( _EQ116, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ116 =  sec7 &  started
         #  _LC6_C14 & !reset & !started;

-- Node name is ':744' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = DFFE( _EQ117, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ117 =  sec6 &  started
         #  _LC6_C15 & !reset & !started;

-- Node name is ':745' 
-- Equation name is '_LC7_C24', type is buried 
_LC7_C24 = DFFE( _EQ118, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ118 =  sec5 &  started
         #  _LC7_C24 & !reset & !started;

-- Node name is ':746' 
-- Equation name is '_LC4_C18', type is buried 
_LC4_C18 = DFFE( _EQ119, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ119 =  sec4 &  started
         #  _LC4_C18 & !reset & !started;

-- Node name is ':771' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = DFFE( _EQ120, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ120 =  sec3 &  started
         #  _LC8_C12 & !reset & !started;

-- Node name is ':772' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = DFFE( _EQ121, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ121 =  sec2 &  started
         #  _LC1_C16 & !reset & !started;

-- Node name is ':773' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = DFFE( _EQ122, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ122 =  sec1 &  started
         #  _LC7_C15 & !reset & !started;

-- Node name is ':774' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = DFFE( _EQ123, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ123 =  sec0 &  started
         #  _LC6_C21 & !reset & !started;



Project Information      e:\amj\eda\2003\experiment\clkscan\clkscan3\time1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:03
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 28,297K

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