time1.rpt

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

-- Equation name is 'min5', location is LC6_C22, type is buried.
min5     = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC3_C22
         #  _LC4_C22 &  min5 & !reset;

-- Node name is ':444' = 'min6' 
-- Equation name is 'min6', location is LC1_C22, type is buried.
min6     = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  _LC7_C22
         #  _LC8_C22 &  min6 & !reset;

-- Node name is ':443' = 'min7' 
-- Equation name is 'min7', location is LC7_C20, type is buried.
min7     = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !_LC1_C20 &  _LC5_C20 &  started
         #  _LC6_C20 & !started;

-- Node name is 'reg10' 
-- Equation name is 'reg10', type is output 
reg10    =  _LC5_C9;

-- Node name is 'reg11' 
-- Equation name is 'reg11', type is output 
reg11    =  _LC3_C9;

-- Node name is 'reg12' 
-- Equation name is 'reg12', type is output 
reg12    =  _LC8_C21;

-- Node name is 'reg13' 
-- Equation name is 'reg13', type is output 
reg13    =  _LC1_C5;

-- Node name is 'reg20' 
-- Equation name is 'reg20', type is output 
reg20    =  _LC4_C21;

-- Node name is 'reg21' 
-- Equation name is 'reg21', type is output 
reg21    =  _LC1_C14;

-- Node name is 'reg22' 
-- Equation name is 'reg22', type is output 
reg22    =  _LC6_C9;

-- Node name is 'reg23' 
-- Equation name is 'reg23', type is output 
reg23    =  _LC5_C21;

-- Node name is 'reg30' 
-- Equation name is 'reg30', type is output 
reg30    =  _LC8_C17;

-- Node name is 'reg31' 
-- Equation name is 'reg31', type is output 
reg31    =  _LC7_C21;

-- Node name is 'reg32' 
-- Equation name is 'reg32', type is output 
reg32    =  _LC1_C12;

-- Node name is 'reg33' 
-- Equation name is 'reg33', type is output 
reg33    =  _LC8_C20;

-- Node name is 'reg40' 
-- Equation name is 'reg40', type is output 
reg40    =  _LC2_C21;

-- Node name is 'reg41' 
-- Equation name is 'reg41', type is output 
reg41    =  _LC3_C21;

-- Node name is 'reg42' 
-- Equation name is 'reg42', type is output 
reg42    =  _LC2_C24;

-- Node name is 'reg43' 
-- Equation name is 'reg43', type is output 
reg43    =  _LC6_C12;

-- Node name is 'reg50' 
-- Equation name is 'reg50', type is output 
reg50    =  _LC4_C18;

-- Node name is 'reg51' 
-- Equation name is 'reg51', type is output 
reg51    =  _LC7_C24;

-- Node name is 'reg52' 
-- Equation name is 'reg52', type is output 
reg52    =  _LC6_C15;

-- Node name is 'reg53' 
-- Equation name is 'reg53', type is output 
reg53    =  _LC6_C14;

-- Node name is 'reg60' 
-- Equation name is 'reg60', type is output 
reg60    =  _LC6_C21;

-- Node name is 'reg61' 
-- Equation name is 'reg61', type is output 
reg61    =  _LC7_C15;

-- Node name is 'reg62' 
-- Equation name is 'reg62', type is output 
reg62    =  _LC1_C16;

-- Node name is 'reg63' 
-- Equation name is 'reg63', type is output 
reg63    =  _LC8_C12;

-- Node name is ':242' = 'sec0' 
-- Equation name is 'sec0', location is LC1_C21, type is buried.
sec0     = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 = !sec0 &  started
         # !reset &  sec0 & !started;

-- Node name is ':241' = 'sec1' 
-- Equation name is 'sec1', location is LC8_C15, type is buried.
sec1     = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 = !reset &  sec1 & !started
         #  _LC2_C15;

-- Node name is ':240' = 'sec2' 
-- Equation name is 'sec2', location is LC5_C16, type is buried.
sec2     = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 = !reset &  sec2 & !started
         #  _LC4_C16;

-- Node name is ':239' = 'sec3' 
-- Equation name is 'sec3', location is LC2_C16, type is buried.
sec3     = DFFE( _EQ020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ020 = !reset &  sec3 & !started
         #  _LC8_C16;

-- Node name is ':238' = 'sec4' 
-- Equation name is 'sec4', location is LC1_C18, type is buried.
sec4     = DFFE( _EQ021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ021 =  _LC5_C18
         #  _LC6_C18 & !reset &  sec4;

-- Node name is ':237' = 'sec5' 
-- Equation name is 'sec5', location is LC1_C24, type is buried.
sec5     = DFFE( _EQ022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ022 = !reset &  sec5 & !started
         #  _LC4_C24 &  started;

-- Node name is ':236' = 'sec6' 
-- Equation name is 'sec6', location is LC3_C15, type is buried.
sec6     = DFFE( _EQ023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ023 = !reset &  sec6 & !started
         #  _LC5_C15 &  started;

-- Node name is ':235' = 'sec7' 
-- Equation name is 'sec7', location is LC7_C14, type is buried.
sec7     = DFFE( _EQ024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ024 = !reset &  sec7 & !started
         #  _LC5_C14 &  started;

-- Node name is ':29' = 'started' 
-- Equation name is 'started', location is LC2_C10, type is buried.
started  = DFFE( VCC, GLOBAL( clk), GLOBAL(!reset), GLOBAL(!start),  start);

-- Node name is '|lpm_add_sub:775|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C24', type is buried 
_LC6_C24 = LCELL( _EQ025);
  _EQ025 =  sec4 &  sec5;

-- Node name is '|lpm_add_sub:775|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = LCELL( _EQ026);
  _EQ026 =  sec4 &  sec5 &  sec6;

-- Node name is '|lpm_add_sub:777|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C24', type is buried 
_LC5_C24 = LCELL( _EQ027);
  _EQ027 =  min0 &  min1;

-- Node name is '|lpm_add_sub:777|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = LCELL( _EQ028);
  _EQ028 =  min0 &  min1 &  min2;

-- Node name is '|lpm_add_sub:778|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ029);
  _EQ029 =  min4 &  min5 &  min6;

-- Node name is '|lpm_add_sub:779|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = LCELL( _EQ030);
  _EQ030 =  hour4 &  hour5;

-- Node name is '~42~1' 
-- Equation name is '~42~1', location is LC2_C20, type is buried.
-- synthesized logic cell 
!_LC2_C20 = _LC2_C20~NOT;
_LC2_C20~NOT = LCELL( _EQ031);
  _EQ031 = !min6
         #  min7
         #  min5;

-- Node name is '~42~2' 
-- Equation name is '~42~2', location is LC5_C17, type is buried.
-- synthesized logic cell 
_LC5_C17 = LCELL( _EQ032);
  _EQ032 =  _LC4_C23 &  _LC8_C14 & !min4 &  started;

-- Node name is '~42~3' 
-- Equation name is '~42~3', location is LC3_C6, type is buried.
-- synthesized logic cell 
_LC3_C6  = LCELL( _EQ033);
  _EQ033 =  _LC1_C20 &  started;

-- Node name is '~42~4' 
-- Equation name is '~42~4', location is LC2_C6, type is buried.
-- synthesized logic cell 
_LC2_C6  = LCELL( _EQ034);
  _EQ034 =  _LC3_C5 &  _LC3_C6;

-- Node name is '~42~5' 
-- Equation name is '~42~5', location is LC6_C5, type is buried.
-- synthesized logic cell 
_LC6_C5  = LCELL( _EQ035);
  _EQ035 =  _LC2_C8 &  _LC3_C5 &  _LC3_C6;

-- Node name is ':42' 
-- Equation name is '_LC1_C20', type is buried 
!_LC1_C20 = _LC1_C20~NOT;
_LC1_C20~NOT = LCELL( _EQ036);
  _EQ036 = !min4
         # !_LC4_C23
         # !_LC2_C20;

-- Node name is '~51~1' 
-- Equation name is '~51~1', location is LC2_C14, type is buried.
-- synthesized logic cell 
!_LC2_C14 = _LC2_C14~NOT;
_LC2_C14~NOT = LCELL( _EQ037);
  _EQ037 = !sec6
         #  sec7
         #  sec5;

-- Node name is ':51' 
-- Equation name is '_LC8_C14', type is buried 
!_LC8_C14 = _LC8_C14~NOT;
_LC8_C14~NOT = LCELL( _EQ038);
  _EQ038 = !sec4
         # !_LC2_C14
         # !_LC7_C16;

-- Node name is ':69' 
-- Equation name is '_LC7_C16', type is buried 
!_LC7_C16 = _LC7_C16~NOT;
_LC7_C16~NOT = LCELL( _EQ039);
  _EQ039 =  sec1
         # !sec3
         #  sec2
         # !sec0;

-- Node name is ':111' 
-- Equation name is '_LC4_C14', type is buried 
_LC4_C14 = LCELL( _EQ040);
  _EQ040 = !_LC3_C14 &  _LC7_C16 &  sec7
         #  _LC3_C14 &  _LC7_C16 & !sec7
         # !_LC7_C16 & !reset &  sec7;

-- Node name is ':112' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ041);
  _EQ041 = !_LC6_C24 &  _LC7_C16 &  sec6
         #  _LC6_C24 &  _LC7_C16 & !sec6
         # !_LC7_C16 & !reset &  sec6;

-- Node name is ':113' 
-- Equation name is '_LC3_C24', type is buried 
_LC3_C24 = LCELL( _EQ042);
  _EQ042 =  _LC7_C16 & !sec4 &  sec5
         #  _LC7_C16 &  sec4 & !sec5
         # !_LC7_C16 & !reset &  sec5;

-- Node name is ':202' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ043);
  _EQ043 =  _LC4_C14 & !_LC8_C14;

-- Node name is ':203' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ044);
  _EQ044 =  _LC4_C15 & !_LC8_C14;

-- Node name is ':204' 
-- Equation name is '_LC4_C24', type is buried 
_LC4_C24 = LCELL( _EQ045);
  _EQ045 =  _LC3_C24 & !_LC8_C14;

-- Node name is '~214~1' 
-- Equation name is '~214~1', location is LC6_C16, type is buried.
-- synthesized logic cell 
_LC6_C16 = LCELL( _EQ046);
  _EQ046 = !sec0 &  sec3