📄 time1.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time1.rpt
time1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 24 AND2 0 2 0 1 |lpm_add_sub:775|addcore:adder|:55
- 3 - C 14 AND2 0 3 0 1 |lpm_add_sub:775|addcore:adder|:59
- 5 - C 24 AND2 0 2 0 1 |lpm_add_sub:777|addcore:adder|:55
- 6 - C 23 AND2 0 3 0 1 |lpm_add_sub:777|addcore:adder|:59
- 3 - C 20 AND2 0 3 0 1 |lpm_add_sub:778|addcore:adder|:59
- 4 - C 11 AND2 0 2 0 1 |lpm_add_sub:779|addcore:adder|:55
- 2 - C 10 DFFE + 1 0 0 54 started (:29)
- 2 - C 20 OR2 s ! 0 3 0 1 ~42~1
- 5 - C 17 AND2 s 0 4 0 1 ~42~2
- 3 - C 06 AND2 s 0 2 0 5 ~42~3
- 2 - C 06 AND2 s 0 2 0 1 ~42~4
- 6 - C 05 AND2 s 0 3 0 2 ~42~5
- 1 - C 20 OR2 ! 0 3 0 18 :42
- 2 - C 14 OR2 s ! 0 3 0 1 ~51~1
- 8 - C 14 OR2 ! 0 3 0 28 :51
- 7 - C 16 OR2 ! 0 4 0 8 :69
- 4 - C 14 OR2 1 3 0 1 :111
- 4 - C 15 OR2 1 3 0 1 :112
- 3 - C 24 OR2 1 3 0 1 :113
- 5 - C 14 AND2 0 2 0 1 :202
- 5 - C 15 AND2 0 2 0 1 :203
- 4 - C 24 AND2 0 2 0 1 :204
- 6 - C 16 OR2 s 0 4 0 1 ~214~1
- 8 - C 16 OR2 0 4 0 1 :214
- 3 - C 16 OR2 s 0 4 0 1 ~215~1
- 4 - C 16 OR2 0 4 0 1 :215
- 1 - C 15 OR2 s 0 3 0 1 ~216~1
- 2 - C 15 OR2 0 4 0 1 :216
- 6 - C 18 OR2 s 0 3 0 1 ~230~1
- 7 - C 14 DFFE + 1 2 0 3 sec7 (:235)
- 3 - C 15 DFFE + 1 2 0 4 sec6 (:236)
- 1 - C 24 DFFE + 1 2 0 5 sec5 (:237)
- 1 - C 18 DFFE + 1 2 0 6 sec4 (:238)
- 2 - C 16 DFFE + 1 2 0 3 sec3 (:239)
- 5 - C 16 DFFE + 1 2 0 4 sec2 (:240)
- 8 - C 15 DFFE + 1 2 0 5 sec1 (:241)
- 1 - C 21 DFFE + 1 1 0 5 sec0 (:242)
- 4 - C 23 OR2 ! 0 4 0 12 :243
- 6 - C 20 AND2 1 1 0 1 :261
- 2 - C 17 AND2 1 1 0 1 :266
- 7 - C 23 OR2 1 3 0 1 :298
- 8 - C 24 OR2 1 3 0 1 :299
- 2 - C 23 OR2 1 3 0 1 :300
- 4 - C 20 OR2 1 3 0 1 :327
- 5 - C 20 OR2 1 3 0 1 :352
- 6 - C 17 AND2 s 1 1 0 1 ~394~1
- 3 - C 18 AND2 s 0 1 0 3 ~414~1
- 5 - C 18 AND2 s 0 4 0 1 ~414~2
- 8 - C 18 AND2 s 0 3 0 1 ~414~3
- 3 - C 23 OR2 0 4 0 1 :416
- 1 - C 13 OR2 s 0 3 0 1 ~422~1
- 8 - C 23 OR2 0 4 0 1 :422
- 5 - C 22 OR2 s 0 4 0 1 ~436~1
- 7 - C 22 AND2 s 0 4 0 1 ~436~2
- 8 - C 22 OR2 s 0 4 0 1 ~436~3
- 2 - C 22 OR2 s 0 4 0 1 ~437~1
- 3 - C 22 AND2 s 0 3 0 1 ~437~2
- 4 - C 22 OR2 s 0 4 0 1 ~437~3
- 4 - C 17 OR2 s 0 3 0 1 ~438~1
- 7 - C 17 OR2 s 0 4 0 1 ~438~2
- 7 - C 18 OR2 s 1 3 0 1 ~442~1
- 7 - C 20 DFFE + 0 4 0 5 min7 (:443)
- 1 - C 22 DFFE + 1 2 0 4 min6 (:444)
- 6 - C 22 DFFE + 1 2 0 5 min5 (:445)
- 3 - C 17 DFFE + 1 2 0 7 min4 (:446)
- 1 - C 23 DFFE + 1 2 0 3 min3 (:447)
- 1 - C 17 DFFE + 0 4 0 5 min2 (:448)
- 5 - C 23 DFFE + 1 2 0 5 min1 (:449)
- 2 - C 18 DFFE + 0 4 0 7 min0 (:450)
- 2 - C 11 OR2 s 0 3 0 1 ~451~1
- 2 - C 05 OR2 s 0 4 0 1 ~451~2
- 1 - C 11 AND2 1 1 0 1 :464
- 1 - C 09 AND2 1 1 0 1 :465
- 2 - C 08 OR2 ! 0 4 0 4 :488
- 5 - C 11 OR2 1 3 0 1 :512
- 2 - C 09 OR2 1 3 0 1 :513
- 3 - C 05 OR2 s 0 4 0 5 ~535~1
- 8 - C 05 AND2 s 0 2 0 4 ~539~1
- 3 - C 08 OR2 0 4 0 1 :540
- 4 - C 06 AND2 1 2 0 1 :550
- 6 - C 11 OR2 0 4 0 1 :553
- 7 - C 09 OR2 0 4 0 1 :554
- 4 - C 08 OR2 1 3 0 1 :557
- 5 - C 06 OR2 0 4 0 1 :558
- 7 - C 11 OR2 1 3 0 1 :578
- 8 - C 09 OR2 1 3 0 1 :579
- 6 - C 08 OR2 1 3 0 1 :582
- 8 - C 06 OR2 1 3 0 1 :583
- 3 - C 11 OR2 s 0 3 0 1 ~602~1
- 5 - C 05 OR2 s 1 3 0 2 ~605~1
- 7 - C 08 OR2 s 0 4 0 1 ~606~1
- 8 - C 08 AND2 s 0 3 0 1 ~606~2
- 7 - C 06 OR2 s 0 2 0 2 ~609~1
- 7 - C 05 DFFE + 0 3 0 2 hour7 (:610)
- 8 - C 11 DFFE + 1 2 0 6 hour6 (:611)
- 4 - C 09 DFFE + 1 2 0 7 hour5 (:612)
- 4 - C 05 DFFE + 0 2 0 5 hour4 (:613)
- 1 - C 08 DFFE + 1 2 0 4 hour3 (:614)
- 5 - C 08 DFFE + 1 2 0 7 hour2 (:615)
- 1 - C 06 DFFE + 1 2 0 8 hour1 (:616)
- 6 - C 06 DFFE + 1 2 0 6 hour0 (:617)
- 1 - C 05 DFFE + 1 2 1 0 :631
- 8 - C 21 DFFE + 1 2 1 0 :632
- 3 - C 09 DFFE + 1 2 1 0 :633
- 5 - C 09 DFFE + 1 2 1 0 :634
- 5 - C 21 DFFE + 1 2 1 0 :659
- 6 - C 09 DFFE + 1 2 1 0 :660
- 1 - C 14 DFFE + 1 2 1 0 :661
- 4 - C 21 DFFE + 1 2 1 0 :662
- 8 - C 20 DFFE + 1 2 1 0 :687
- 1 - C 12 DFFE + 1 2 1 0 :688
- 7 - C 21 DFFE + 1 2 1 0 :689
- 8 - C 17 DFFE + 1 2 1 0 :690
- 6 - C 12 DFFE + 1 2 1 0 :715
- 2 - C 24 DFFE + 1 2 1 0 :716
- 3 - C 21 DFFE + 1 2 1 0 :717
- 2 - C 21 DFFE + 1 2 1 0 :718
- 6 - C 14 DFFE + 1 2 1 0 :743
- 6 - C 15 DFFE + 1 2 1 0 :744
- 7 - C 24 DFFE + 1 2 1 0 :745
- 4 - C 18 DFFE + 1 2 1 0 :746
- 8 - C 12 DFFE + 1 2 1 0 :771
- 1 - C 16 DFFE + 1 2 1 0 :772
- 7 - C 15 DFFE + 1 2 1 0 :773
- 6 - C 21 DFFE + 1 2 1 0 :774
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time1.rpt
time1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 13/ 96( 13%) 17/ 48( 35%) 22/ 48( 45%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time1.rpt
time1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 49 clk
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time1.rpt
time1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 67 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time1.rpt
time1
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is ':617' = 'hour0'
-- Equation name is 'hour0', location is LC6_C6, type is buried.
hour0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = hour0 & _LC7_C6 & !reset
# !hour0 & _LC2_C6;
-- Node name is ':616' = 'hour1'
-- Equation name is 'hour1', location is LC1_C6, type is buried.
hour1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC8_C6 & started
# hour1 & !reset & !started;
-- Node name is ':615' = 'hour2'
-- Equation name is 'hour2', location is LC5_C8, type is buried.
hour2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC6_C8 & started
# hour2 & !reset & !started;
-- Node name is ':614' = 'hour3'
-- Equation name is 'hour3', location is LC1_C8, type is buried.
hour3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC8_C8
# hour3 & _LC7_C6 & !reset;
-- Node name is ':613' = 'hour4'
-- Equation name is 'hour4', location is LC4_C5, type is buried.
hour4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = hour4 & _LC5_C5
# !hour4 & _LC6_C5;
-- Node name is ':612' = 'hour5'
-- Equation name is 'hour5', location is LC4_C9, type is buried.
hour5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC8_C9 & started
# hour5 & !reset & !started;
-- Node name is ':611' = 'hour6'
-- Equation name is 'hour6', location is LC8_C11, type is buried.
hour6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC7_C11 & started
# hour6 & !reset & !started;
-- Node name is ':610' = 'hour7'
-- Equation name is 'hour7', location is LC7_C5, type is buried.
hour7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = hour7 & _LC5_C5
# !hour7 & !_LC3_C11 & _LC6_C5
# hour7 & _LC3_C11 & _LC6_C5;
-- Node name is ':450' = 'min0'
-- Equation name is 'min0', location is LC2_C18, type is buried.
min0 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC7_C18
# !_LC1_C20 & _LC8_C14 & _LC8_C18;
-- Node name is ':449' = 'min1'
-- Equation name is 'min1', location is LC5_C23, type is buried.
min1 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC3_C23 & started
# min1 & !reset & !started;
-- Node name is ':448' = 'min2'
-- Equation name is 'min2', location is LC1_C17, type is buried.
min2 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC2_C17 & !started
# !_LC4_C23 & _LC8_C24 & started;
-- Node name is ':447' = 'min3'
-- Equation name is 'min3', location is LC1_C23, type is buried.
min3 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC8_C23
# min3 & !reset & !started;
-- Node name is ':446' = 'min4'
-- Equation name is 'min4', location is LC3_C17, type is buried.
min4 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC4_C17 & min4 & !reset
# _LC7_C17;
-- Node name is ':445' = 'min5'
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