clkscan3.rpt

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

_LC1_B23 = LCELL( _EQ012);
  _EQ012 =  sec1 &  state0 & !state1 &  state2;

-- Node name is ':229' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ013);
  _EQ013 =  sec0 &  state0 & !state1 &  state2;

-- Node name is ':234' 
-- Equation name is '_LC6_B13', type is buried 
!_LC6_B13 = _LC6_B13~NOT;
_LC6_B13~NOT = LCELL( _EQ014);
  _EQ014 =  state0 &  state1 &  state2;

-- Node name is '~240~1' 
-- Equation name is '~240~1', location is LC5_B24, type is buried.
-- synthesized logic cell 
_LC5_B24 = LCELL( _EQ015);
  _EQ015 =  _LC8_B24 &  sec7
         #  _LC7_B24 &  min3;

-- Node name is '~240~2' 
-- Equation name is '~240~2', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ016);
  _EQ016 =  _LC1_B13 & !_LC6_B13
         #  _LC3_B13
         #  _LC5_B24;

-- Node name is '~240~3' 
-- Equation name is '~240~3', location is LC8_B13, type is buried.
-- synthesized logic cell 
_LC8_B13 = LCELL( _EQ017);
  _EQ017 =  hour3 &  _LC4_B13
         #  hour7 &  _LC2_B23;

-- Node name is '~241~1' 
-- Equation name is '~241~1', location is LC6_B24, type is buried.
-- synthesized logic cell 
_LC6_B24 = LCELL( _EQ018);
  _EQ018 =  _LC8_B24 &  sec6
         #  _LC7_B24 &  min2;

-- Node name is '~241~2' 
-- Equation name is '~241~2', location is LC3_B24, type is buried.
-- synthesized logic cell 
_LC3_B24 = LCELL( _EQ019);
  _EQ019 =  _LC3_B23 & !_LC6_B13
         #  _LC4_B24
         #  _LC6_B24;

-- Node name is '~241~3' 
-- Equation name is '~241~3', location is LC8_B23, type is buried.
-- synthesized logic cell 
_LC8_B23 = LCELL( _EQ020);
  _EQ020 =  hour2 &  _LC4_B13
         #  hour6 &  _LC2_B23;

-- Node name is '~242~1' 
-- Equation name is '~242~1', location is LC4_B23, type is buried.
-- synthesized logic cell 
_LC4_B23 = LCELL( _EQ021);
  _EQ021 =  _LC8_B24 &  sec5
         #  _LC7_B24 &  min1;

-- Node name is '~242~2' 
-- Equation name is '~242~2', location is LC6_B23, type is buried.
-- synthesized logic cell 
_LC6_B23 = LCELL( _EQ022);
  _EQ022 =  _LC5_B23 & !_LC6_B13
         #  _LC1_B23
         #  _LC4_B23;

-- Node name is '~242~3' 
-- Equation name is '~242~3', location is LC7_B23, type is buried.
-- synthesized logic cell 
_LC7_B23 = LCELL( _EQ023);
  _EQ023 =  hour1 &  _LC4_B13
         #  hour5 &  _LC2_B23;

-- Node name is '~243~1' 
-- Equation name is '~243~1', location is LC5_B15, type is buried.
-- synthesized logic cell 
_LC5_B15 = LCELL( _EQ024);
  _EQ024 =  _LC8_B24 &  sec4
         #  _LC7_B24 &  min0;

-- Node name is '~243~2' 
-- Equation name is '~243~2', location is LC6_B15, type is buried.
-- synthesized logic cell 
_LC6_B15 = LCELL( _EQ025);
  _EQ025 = !_LC6_B13 &  _LC8_B15
         #  _LC2_B15
         #  _LC5_B15;

-- Node name is '~243~3' 
-- Equation name is '~243~3', location is LC7_B15, type is buried.
-- synthesized logic cell 
_LC7_B15 = LCELL( _EQ026);
  _EQ026 =  hour0 &  _LC4_B13
         #  hour4 &  _LC2_B23;

-- Node name is ':244' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = DFFE( _EQ027, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ027 =  _LC5_B13
         #  _LC3_B15 &  min7
         #  _LC8_B13;

-- Node name is ':245' 
-- Equation name is '_LC3_B23', type is buried 
_LC3_B23 = DFFE( _EQ028, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ028 =  _LC3_B24
         #  _LC3_B15 &  min6
         #  _LC8_B23;

-- Node name is ':246' 
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = DFFE( _EQ029, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ029 =  _LC6_B23
         #  _LC3_B15 &  min5
         #  _LC7_B23;

-- Node name is ':247' 
-- Equation name is '_LC8_B15', type is buried 
_LC8_B15 = DFFE( _EQ030, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ030 =  _LC6_B15
         #  _LC3_B15 &  min4
         #  _LC7_B15;

-- Node name is ':292' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = DFFE( _EQ031, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ031 =  state0 & !state1 &  state2
         #  _LC2_B24 &  state0 &  state2;

-- Node name is ':293' 
-- Equation name is '_LC3_B19', type is buried 
_LC3_B19 = DFFE( _EQ032, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ032 =  _LC3_B19 & !_LC6_B13
         #  _LC8_B24;

-- Node name is ':294' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = DFFE( _EQ033, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ033 =  _LC1_B24 & !_LC6_B13
         #  _LC7_B24;

-- Node name is ':295' 
-- Equation name is '_LC2_B19', type is buried 
_LC2_B19 = DFFE( _EQ034, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ034 =  _LC3_B15
         #  _LC2_B19 & !_LC6_B13;

-- Node name is ':296' 
-- Equation name is '_LC5_B19', type is buried 
_LC5_B19 = DFFE( _EQ035, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ035 =  _LC4_B13
         #  _LC5_B19 & !_LC6_B13;

-- Node name is ':297' 
-- Equation name is '_LC6_B19', type is buried 
_LC6_B19 = DFFE( _EQ036, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ036 =  _LC2_B23
         # !_LC6_B13 &  _LC6_B19;



Project Information   e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,675K