📄 clkscan3.rpt
字号:
65 - - B -- OUTPUT 0 1 0 0 scan_en2
22 - - B -- OUTPUT 0 1 0 0 scan_en3
60 - - C -- OUTPUT 0 1 0 0 scan_en4
72 - - A -- OUTPUT 0 1 0 0 scan_en5
61 - - C -- OUTPUT 0 1 0 0 scan_en6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3.rpt
clkscan3
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 23 OR2 0 3 0 5 :36
- 4 - B 13 AND2 0 3 0 5 :66
- 3 - B 15 AND2 0 3 0 5 :91
- 7 - B 24 AND2 0 3 0 6 :116
- 8 - B 24 AND2 0 3 0 6 :141
- 4 - B 15 DFFE + 0 4 0 14 state2 (:194)
- 2 - B 13 DFFE + 0 2 0 13 state1 (:195)
- 7 - B 13 DFFE + 0 2 0 13 state0 (:196)
- 1 - B 15 AND2 0 2 0 1 :200
- 3 - B 13 AND2 1 3 0 1 :226
- 4 - B 24 AND2 1 3 0 1 :227
- 1 - B 23 AND2 1 3 0 1 :228
- 2 - B 15 AND2 1 3 0 1 :229
- 6 - B 13 AND2 ! 0 3 0 9 :234
- 5 - B 24 OR2 s 2 2 0 1 ~240~1
- 5 - B 13 OR2 s 0 4 0 1 ~240~2
- 8 - B 13 OR2 s 2 2 0 1 ~240~3
- 6 - B 24 OR2 s 2 2 0 1 ~241~1
- 3 - B 24 OR2 s 0 4 0 1 ~241~2
- 8 - B 23 OR2 s 2 2 0 1 ~241~3
- 4 - B 23 OR2 s 2 2 0 1 ~242~1
- 6 - B 23 OR2 s 0 4 0 1 ~242~2
- 7 - B 23 OR2 s 2 2 0 1 ~242~3
- 5 - B 15 OR2 s 2 2 0 1 ~243~1
- 6 - B 15 OR2 s 0 4 0 1 ~243~2
- 7 - B 15 OR2 s 2 2 0 1 ~243~3
- 1 - B 13 DFFE + 1 3 1 1 :244
- 3 - B 23 DFFE + 1 3 1 1 :245
- 5 - B 23 DFFE + 1 3 1 1 :246
- 8 - B 15 DFFE + 1 3 1 1 :247
- 2 - B 24 DFFE + 0 3 1 0 :292
- 3 - B 19 DFFE + 0 2 1 0 :293
- 1 - B 24 DFFE + 0 2 1 0 :294
- 2 - B 19 DFFE + 0 2 1 0 :295
- 5 - B 19 DFFE + 0 2 1 0 :296
- 6 - B 19 DFFE + 0 2 1 0 :297
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3.rpt
clkscan3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 15/ 96( 15%) 0/ 48( 0%) 20/ 48( 41%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3.rpt
clkscan3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3.rpt
clkscan3
** EQUATIONS **
clk : INPUT;
hour0 : INPUT;
hour1 : INPUT;
hour2 : INPUT;
hour3 : INPUT;
hour4 : INPUT;
hour5 : INPUT;
hour6 : INPUT;
hour7 : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min4 : INPUT;
min5 : INPUT;
min6 : INPUT;
min7 : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec4 : INPUT;
sec5 : INPUT;
sec6 : INPUT;
sec7 : INPUT;
-- Node name is 'scan_data0'
-- Equation name is 'scan_data0', type is output
scan_data0 = _LC8_B15;
-- Node name is 'scan_data1'
-- Equation name is 'scan_data1', type is output
scan_data1 = _LC5_B23;
-- Node name is 'scan_data2'
-- Equation name is 'scan_data2', type is output
scan_data2 = _LC3_B23;
-- Node name is 'scan_data3'
-- Equation name is 'scan_data3', type is output
scan_data3 = _LC1_B13;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC6_B19;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC5_B19;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC2_B19;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC1_B24;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC3_B19;
-- Node name is 'scan_en6'
-- Equation name is 'scan_en6', type is output
scan_en6 = _LC2_B24;
-- Node name is ':196' = 'state0'
-- Equation name is 'state0', location is LC7_B13, type is buried.
state0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !state0
# state1 & state2;
-- Node name is ':195' = 'state1'
-- Equation name is 'state1', location is LC2_B13, type is buried.
state1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !state0 & state1 & !state2
# state0 & !state1;
-- Node name is ':194' = 'state2'
-- Equation name is 'state2', location is LC4_B15, type is buried.
state2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC8_B24
# _LC7_B24
# _LC1_B15 & state0;
-- Node name is ':36'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ004);
_EQ004 = !state0 & state1 & state2
# !state0 & !state1 & !state2;
-- Node name is ':66'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ005);
_EQ005 = state0 & !state1 & !state2;
-- Node name is ':91'
-- Equation name is '_LC3_B15', type is buried
_LC3_B15 = LCELL( _EQ006);
_EQ006 = !state0 & state1 & !state2;
-- Node name is ':116'
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = LCELL( _EQ007);
_EQ007 = state0 & state1 & !state2;
-- Node name is ':141'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = LCELL( _EQ008);
_EQ008 = !state0 & !state1 & state2;
-- Node name is ':200'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = LCELL( _EQ009);
_EQ009 = !state1 & state2;
-- Node name is ':226'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ010);
_EQ010 = sec3 & state0 & !state1 & state2;
-- Node name is ':227'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = LCELL( _EQ011);
_EQ011 = sec2 & state0 & !state1 & state2;
-- Node name is ':228'
-- Equation name is '_LC1_B23', type is buried
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -