lib.dls

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块

DLSL
1
clkdiv.VerilogView U2294093.DLS
clkdiv2.VerilogView U6020997.DLS
clkscan3.VerilogView U0555328.DLS
p7segment.VerilogView U6955853.DLS
scan.VerilogView U4278454.DLS
time1.VerilogView U1072186.DLS
time2.VerilogView U3863846.DLS
timer.VerilogView U0127638.DLS