config_controller.fit.eqn

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。

--u5 is u5 at LC94
u5_or_out = VCC;
u5_reg_input = u5_or_out;
u5 = DFFE(u5_reg_input, GLOBAL(cpld_clkosc), reset_n, , );


--F1_dffs[0] is dclk_divider:u1|lpm_counter:lpm_counter_component|dffs[0] at LC103
F1_dffs[0]_reg_input = VCC;
F1_dffs[0] = TFFE(F1_dffs[0]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , );


--F1_dffs[1] is dclk_divider:u1|lpm_counter:lpm_counter_component|dffs[1] at LC106
F1_dffs[1]_reg_input = VCC;
F1_dffs[1] = TFFE(F1_dffs[1]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F1_dffs[0]);


--F1_dffs[2] is dclk_divider:u1|lpm_counter:lpm_counter_component|dffs[2] at LC48
F1_dffs[2]_reg_input = VCC;
F1_dffs[2]_p3_out = F1_dffs[1] & F1_dffs[0];
F1_dffs[2] = TFFE(F1_dffs[2]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F1_dffs[2]_p3_out);


--F1_dffs[3] is dclk_divider:u1|lpm_counter:lpm_counter_component|dffs[3] at LC44
F1_dffs[3]_reg_input = VCC;
F1_dffs[3]_p3_out = F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F1_dffs[3] = TFFE(F1_dffs[3]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F1_dffs[3]_p3_out);


--u10 is u10 at LC112
u10_or_out = !status_n;
u10_reg_input = u10_or_out;
u10_p3_out = F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
u10 = DFFE(u10_reg_input, GLOBAL(cpld_clkosc), !A1L45, , u10_p3_out);


--u13 is u13 at LC8
u13_or_out = VCC;
u13_reg_input = u13_or_out;
u13_p3_out = F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
u13 = DFFE(u13_reg_input, GLOBAL(cpld_clkosc), !A1L45, , u13_p3_out);


--u11 is u11 at LC111
u11_or_out = VCC;
u11_reg_input = u11_or_out;
u11_p3_out = F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0] & config_done;
u11 = DFFE(u11_reg_input, GLOBAL(cpld_clkosc), !A1L45, , u11_p3_out);


--u12 is u12 at LC98
u12_p1_out = !u8 & u13 & !config_done & !u10;
u12_or_out = u12_p1_out;
u12_reg_input = u12_or_out;
u12_p3_out = F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
u12 = DFFE(u12_reg_input, GLOBAL(cpld_clkosc), !A1L45, , u12_p3_out);


--A1L63 is dclkq3_stcntg~8 at LC9
A1L63_p1_out = u12 & F1_dffs[3];
A1L63_or_out = A1L63_p1_out;
A1L63 = A1L63_or_out;


--F3_dffs[0] is data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[0] at LC42
F3_dffs[0]_reg_input = VCC;
F3_dffs[0]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F3_dffs[0] = TFFE(F3_dffs[0]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F3_dffs[0]_p3_out);


--F3_dffs[1] is data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[1] at LC36
F3_dffs[1]_reg_input = VCC;
F3_dffs[1]_p3_out = F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F3_dffs[1] = TFFE(F3_dffs[1]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F3_dffs[1]_p3_out);


--F3_dffs[2] is data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] at LC34
F3_dffs[2]_reg_input = VCC;
F3_dffs[2]_p3_out = F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F3_dffs[2] = TFFE(F3_dffs[2]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F3_dffs[2]_p3_out);


--F2_dffs[0] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[0] at LC3
F2_dffs[0]_reg_input = VCC;
F2_dffs[0]_p3_out = F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[0] = TFFE(F2_dffs[0]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[0]_p3_out);


--G1_dffs[6] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[6] at LC108
G1_dffs[6]_p1_out = F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !D[7];
G1_dffs[6]_or_out = G1_dffs[6]_p1_out;
G1_dffs[6]_reg_input = !(G1_dffs[6]_or_out);
G1_dffs[6]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[6] = DFFE(G1_dffs[6]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[6]_p3_out);


--F2_dffs[1] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[1] at LC1
F2_dffs[1]_reg_input = VCC;
F2_dffs[1]_p3_out = F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[1] = TFFE(F2_dffs[1]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[1]_p3_out);


--G1_dffs[5] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[5] at LC104
G1_dffs[5]_p0_out = !D[6] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & G1_dffs[6];
G1_dffs[5]_p4_out = D[6] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !G1_dffs[6];
G1_dffs[5]_or_out = G1_dffs[5]_p0_out # G1_dffs[5]_p4_out;
G1_dffs[5]_reg_input = G1_dffs[6] $ G1_dffs[5]_or_out;
G1_dffs[5]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[5] = DFFE(G1_dffs[5]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[5]_p3_out);


--F2_dffs[2] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[2] at LC30
F2_dffs[2]_reg_input = VCC;
F2_dffs[2]_p3_out = F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[2] = TFFE(F2_dffs[2]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[2]_p3_out);


--F2_dffs[3] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[3] at LC29
F2_dffs[3]_reg_input = VCC;
F2_dffs[3]_p3_out = F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[3] = TFFE(F2_dffs[3]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[3]_p3_out);


--G1_dffs[4] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[4] at LC110
G1_dffs[4]_p0_out = !D[5] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & G1_dffs[5];
G1_dffs[4]_p4_out = D[5] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !G1_dffs[5];
G1_dffs[4]_or_out = G1_dffs[4]_p0_out # G1_dffs[4]_p4_out;
G1_dffs[4]_reg_input = G1_dffs[5] $ G1_dffs[4]_or_out;
G1_dffs[4]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[4] = DFFE(G1_dffs[4]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[4]_p3_out);


--F2_dffs[4] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[4] at LC27
F2_dffs[4]_reg_input = VCC;
F2_dffs[4]_p3_out = F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[4] = TFFE(F2_dffs[4]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[4]_p3_out);


--G1_dffs[3] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[3] at LC100
G1_dffs[3]_p0_out = !D[4] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & G1_dffs[4];
G1_dffs[3]_p4_out = D[4] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !G1_dffs[4];
G1_dffs[3]_or_out = G1_dffs[3]_p0_out # G1_dffs[3]_p4_out;
G1_dffs[3]_reg_input = G1_dffs[4] $ G1_dffs[3]_or_out;
G1_dffs[3]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[3] = DFFE(G1_dffs[3]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[3]_p3_out);


--F2_dffs[5] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[5] at LC25
F2_dffs[5]_reg_input = VCC;
F2_dffs[5]_p3_out = F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[5] = TFFE(F2_dffs[5]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[5]_p3_out);


--G1_dffs[2] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[2] at LC5
G1_dffs[2]_p0_out = !D[3] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & G1_dffs[3];
G1_dffs[2]_p4_out = D[3] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !G1_dffs[3];
G1_dffs[2]_or_out = G1_dffs[2]_p0_out # G1_dffs[2]_p4_out;
G1_dffs[2]_reg_input = G1_dffs[3] $ G1_dffs[2]_or_out;
G1_dffs[2]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[2] = DFFE(G1_dffs[2]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[2]_p3_out);


--F2_dffs[6] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[6] at LC24
F2_dffs[6]_reg_input = VCC;
F2_dffs[6]_p3_out = F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[6] = TFFE(F2_dffs[6]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[6]_p3_out);


--F2_dffs[7] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[7] at LC22
F2_dffs[7]_reg_input = VCC;
F2_dffs[7]_p3_out = F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[7] = TFFE(F2_dffs[7]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[7]_p3_out);


--G1_dffs[1] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] at LC2
G1_dffs[1]_p0_out = !D[2] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & G1_dffs[2];
G1_dffs[1]_p4_out = D[2] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !G1_dffs[2];
G1_dffs[1]_or_out = G1_dffs[1]_p0_out # G1_dffs[1]_p4_out;
G1_dffs[1]_reg_input = G1_dffs[2] $ G1_dffs[1]_or_out;
G1_dffs[1]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[1] = DFFE(G1_dffs[1]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[1]_p3_out);


--F2_dffs[8] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[8] at LC21
F2_dffs[8]_reg_input = VCC;
F2_dffs[8]_p3_out = F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[8] = TFFE(F2_dffs[8]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[8]_p3_out);


--G1_dffs[0] is shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] at LC4
G1_dffs[0]_p0_out = !D[1] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & G1_dffs[1];
G1_dffs[0]_p4_out = D[1] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & !G1_dffs[1];
G1_dffs[0]_or_out = G1_dffs[0]_p0_out # G1_dffs[0]_p4_out;
G1_dffs[0]_reg_input = G1_dffs[1] $ G1_dffs[0]_or_out;
G1_dffs[0]_p3_out = u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
G1_dffs[0] = DFFE(G1_dffs[0]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , G1_dffs[0]_p3_out);


--F2_dffs[9] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[9] at LC19
F2_dffs[9]_reg_input = VCC;
F2_dffs[9]_p3_out = F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[9] = TFFE(F2_dffs[9]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[9]_p3_out);


--A1L43 is data0~50 at LC97
A1L43_p1_out = D[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0];
A1L43_p2_out = !F3_dffs[2] & G1_dffs[0];
A1L43_p3_out = !F3_dffs[1] & G1_dffs[0];
A1L43_p4_out = !F3_dffs[0] & G1_dffs[0];
A1L43_or_out = A1L43_p1_out # A1L43_p2_out # A1L43_p3_out # A1L43_p4_out;
A1L43 = A1L43_or_out;


--F2_dffs[10] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[10] at LC17
F2_dffs[10]_reg_input = VCC;
F2_dffs[10]_p3_out = F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[10] = TFFE(F2_dffs[10]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[10]_p3_out);


--F2_dffs[11] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[11] at LC46
F2_dffs[11]_reg_input = VCC;
F2_dffs[11]_p3_out = F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[11] = TFFE(F2_dffs[11]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[11]_p3_out);


--F2_dffs[12] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[12] at LC45
F2_dffs[12]_reg_input = VCC;
F2_dffs[12]_p3_out = F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[12] = TFFE(F2_dffs[12]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[12]_p3_out);


--F2_dffs[13] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[13] at LC43
F2_dffs[13]_reg_input = VCC;
F2_dffs[13]_p3_out = F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[13] = TFFE(F2_dffs[13]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[13]_p3_out);


--F2_dffs[14] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[14] at LC41
F2_dffs[14]_reg_input = VCC;
F2_dffs[14]_p3_out = F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[14] = TFFE(F2_dffs[14]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[14]_p3_out);


--F2_dffs[15] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[15] at LC40
F2_dffs[15]_reg_input = VCC;
F2_dffs[15]_p3_out = F2_dffs[14] & F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[15] = TFFE(F2_dffs[15]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[15]_p3_out);


--F2_dffs[16] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[16] at LC38
F2_dffs[16]_reg_input = VCC;
F2_dffs[16]_p3_out = F2_dffs[15] & F2_dffs[14] & F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[16] = TFFE(F2_dffs[16]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[16]_p3_out);


--F2_dffs[17] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[17] at LC37
F2_dffs[17]_reg_input = VCC;
F2_dffs[17]_p3_out = F2_dffs[16] & F2_dffs[15] & F2_dffs[14] & F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0];
F2_dffs[17] = TFFE(F2_dffs[17]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[17]_p3_out);


--F2_dffs[18] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[18] at LC35
F2_dffs[18]_reg_input = VCC;
F2_dffs[18]_p3_out = F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0] & F2_dffs[16] & F2_dffs[17] & F2_dffs[15] & F2_dffs[14] & F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0];
F2_dffs[18] = TFFE(F2_dffs[18]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[18]_p3_out);


--F2_dffs[19] is address_counter:u2|lpm_counter:lpm_counter_component|dffs[19] at LC33
F2_dffs[19]_reg_input = VCC;
F2_dffs[19]_p3_out = F2_dffs[18] & F3_dffs[2] & F3_dffs[1] & F3_dffs[0] & u12 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0] & F2_dffs[16] & F2_dffs[17] & F2_dffs[15] & F2_dffs[14] & F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0];
F2_dffs[19] = TFFE(F2_dffs[19]_reg_input, GLOBAL(cpld_clkosc), !A1L45, , F2_dffs[19]_p3_out);


--u9 is u9 at LC39
u9_or_out = VCC;
u9_reg_input = u9_or_out;
u9_p2_out = u5 & A1L55;
u9_p3_out = F2_dffs[19] & F2_dffs[18] & F2_dffs[16] & F2_dffs[17] & F2_dffs[15] & F2_dffs[14] & F2_dffs[13] & F2_dffs[12] & F2_dffs[11] & F2_dffs[10] & F2_dffs[9] & F2_dffs[8] & F2_dffs[7] & F2_dffs[6] & F2_dffs[5] & F2_dffs[4] & F2_dffs[3] & F2_dffs[2] & F2_dffs[1] & F2_dffs[0];
u9 = DFFE(u9_reg_input, GLOBAL(cpld_clkosc), !u9_p2_out, , u9_p3_out);


--A1L55 is restart_sequence~153 at SEXP33
A1L55 = EXP(!u6 & u7);


--u7 is u7 at LC109
u7_p1_out = u12 & !status_n;
u7_p3_out = !u11 & u9;
u7_or_out = u7_p1_out # u7_p3_out;
u7_reg_input = u7_or_out;
u7 = DFFE(u7_reg_input, GLOBAL(cpld_clkosc), u5, , );


--u6 is u6 at LC64
u6_p1_out = !u6 & !u7;
u6_or_out = u6_p1_out;
u6_reg_input = !(u6_or_out);
u6 = DFFE(u6_reg_input, GLOBAL(cpld_clkosc), !reset_n, , );


--u8 is u8 at LC107
u8_p1_out = u9 & u6 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0] & !u8;
u8_p3_out = u6 & F1_dffs[3] & F1_dffs[2] & F1_dffs[1] & F1_dffs[0] & !u8 & u12 & !status_n;
u8_or_out = u8_p1_out # u8_p3_out;
u8_reg_input = u8_or_out;
u8 = TFFE(u8_reg_input, GLOBAL(cpld_clkosc), u5, , );


--A1L17 is user_led~9 at LC102
A1L17_p1_out = !u8 & !u6;
A1L17_or_out = A1L17_p1_out;
A1L17 = A1L17_or_out;


--A1L64 is loading_led~11 at LC99
A1L64_p1_out = !u8 & !u11;
A1L64_or_out = A1L64_p1_out;
A1L64 = A1L64_or_out;


--A1L74 is loading_led~12 at LC56
A1L74_or_out = !A1L64;
A1L74 = A1L74_or_out;


--A1L84 is loading_led~14 at LC59
A1L84_or_out = !A1L64;
A1L84 = A1L84_or_out;


--A1L94 is loading_led~17 at LC105
A1L94_p1_out = u12 & F2_dffs[16] & !u8 & !u11;
A1L94_or_out = A1L94_p1_out # !u5;
A1L94 = A1L94_or_out;


--~GND~0 is ~GND~0 at LC101
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;