📄 config_controller.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY config_controller IS
PORT
(
cpld_clkosc : IN STD_LOGIC ;--从clock发生芯片输入到cpld，
--提供内部晶振时钟
reset_n : IN STD_LOGIC ;--从reset发生芯片输入到cpld
status_n : IN STD_LOGIC ;--从cyclone到cpld，置1表cyclone
--已做好接收配置数据准备；配置
--过程中置0表出错
--config_request_n : IN STD_LOGIC ;--从cyclone输入到cpld，表cyclone
--向cpld请求配置数据
--safe_config_n : IN STD_LOGIC ;--从外部电路到cpld，外部按钮，
--按下即可强迫cpld从flash安全
--区读配置数据
flash_a22 : OUT STD_LOGIC ;--从cpld到flash，接1
flash_a21 : OUT STD_LOGIC ;--从cpld到flash，接1
flash_a20 : OUT STD_LOGIC ;--从cpld到flash，接0选择user，
--接1选择safe
a : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);--从cpld到
--flash，
--1M地址线
D : IN STD_LOGIC_VECTOR (7 DOWNTO 0);--从flash输入
--字节到cpld，
--并行数据输入
pld_data0 : OUT STD_LOGIC ;--从cpld到cyclone，串行输出数据
--到cyclone
config_n : OUT STD_LOGIC ;--从cpld到cyclone;开启配置
config_done : IN STD_LOGIC ;--从cyclone反馈给cpld，以置1表
--示配置完成
DCLK : OUT STD_LOGIC ;--从cpld到cyclone，提供配置时钟
--INIT_DONE :input;--显示cyclone初始化完成，用户可以用配置
--成功的FPGA了
flash_cs_n : OUT STD_LOGIC ;--flash片选信号，置1表选中
flash_oe_n : OUT STD_LOGIC ;--flash使能信号，置1表使能
flash_rw_n : OUT STD_LOGIC ;--flash读信号，置1表只从flash里读
flash_reset_n : OUT STD_LOGIC ;--flash复位信号
--flash_RY_BY_n :input;--用于等待flash
--enet_reset :output;--从cpld输出
--proto1_reset_n :output;--从cpld输出
--proto2_reset_n :output;--从cpld输出
pld_msel0 : OUT STD_LOGIC ;--配置模式选择
pld_msel1 : OUT STD_LOGIC ;--配置模式选择
--pld_cs_n :input;--EPCS片选信号，置1表选中
--pld_asd0 :input;--从cyclong到EPCS,传送控制信号
loading_led : OUT STD_LOGIC ;--从cpld输出，闪灯，显示配置正
--在进行
error_led : OUT STD_LOGIC ;--从cpld输出，报错灯，灯亮表配
--置失败
user_led : OUT STD_LOGIC --从cpld输出，灯亮表从用户区读
--入配置数据的
--safe_led : OUT STD_LOGIC ;--从cpld输出，灯亮表从安全区读
--入配置数据的
--enet_vlbus_n :output;--从cpld输出
--user_pb0 :input;
--user_pb1 :input;
--user_pb2 :input;
--user_pb3 :input;
);
END config_controller;
ARCHITECTURE config OF config_controller IS
COMPONENT dclk_divider--调用子模块dclk_divider
PORT --此模块用于分频产生配置时钟
(
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
cout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT address_counter--调用子模块address_counter
PORT --此模块用于产生flash的读地址
(
clock : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
cout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT data_bit_counter--调用子模块data_bit_counter
PORT --此模块用于分字节为bit流
(
clock : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
cout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT shift_register--调用子模块shift_register
PORT --此模块用于串行读配置数据（bit流）到待配置的FPGA里
(
clock : IN STD_LOGIC ;
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DFFE--调用带有使能的D触发器
PORT (d : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
ena : IN STD_LOGIC;
q : OUT STD_LOGIC );
END COMPONENT;
COMPONENT DFF--调用不带有使能的D触发器
PORT (d : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC );
END COMPONENT;
COMPONENT TRI--调用三态门
PORT (a_in : IN STD_LOGIC;
oe: IN STD_LOGIC;
a_out: OUT STD_LOGIC);
END COMPONENT;
SIGNAL dclk_divider_cout, dclk_divider_q3 : STD_LOGIC ;
SIGNAL address_counter_clk_en, address_counter_cout : STD_LOGIC ;
SIGNAL address_counter_q : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL data_bit_counter_cout : STD_LOGIC ;
SIGNAL shift_register_enable, shift_register_shiftout : STD_LOGIC ;
SIGNAL reset_pulse_q : STD_LOGIC ;
SIGNAL try_user_config_d, try_user_config_q : STD_LOGIC ;
SIGNAL eek_an_error_d, eek_an_error_q : STD_LOGIC ;
SIGNAL state_error_d, state_error_q : STD_LOGIC ;
SIGNAL counter_wrapped_d, counter_wrapped_q : STD_LOGIC ;
SIGNAL state_waiting_for_status_n_q : STD_LOGIC ;
SIGNAL state_done_d, state_done_q : STD_LOGIC ;
SIGNAL state_counting_d, state_counting_q : STD_LOGIC ;
SIGNAL config_n_reg_q : STD_LOGIC ;
SIGNAL data0, restart_sequence, not_restart_sequence : STD_LOGIC ;
SIGNAL not_reset_n, not_status_n, not_reset_pulse_q, drive_outputs : STD_LOGIC ;
SIGNAL not_try_user_config_q, dclkq3_stcntg, not_config_n_reg_q : STD_LOGIC ;
BEGIN
flash_reset_n<=not reset_pulse_q;
--dclk_en<=dclk_divider_cout;
address_counter_clk_en<=dclk_divider_cout and data_bit_counter_cout;
shift_register_enable<=dclk_divider_cout and state_counting_q;
try_user_config_d<=(not eek_an_error_q)and try_user_config_q;
eek_an_error_d<=((not status_n)and state_counting_q) or (counter_wrapped_q and (not state_done_q));
state_error_d<=((((not status_n)and state_counting_q)or counter_wrapped_q)and(not try_user_config_q))or state_error_q;
counter_wrapped_d<=address_counter_cout or counter_wrapped_q;
state_done_d<=config_done or state_done_q;
state_counting_d<=(not config_done)and(not state_waiting_for_status_n_q)and(not state_error_q)and config_n_reg_q;
restart_sequence<=reset_pulse_q or (eek_an_error_q and try_user_config_q);
dclkq3_stcntg<=dclk_divider_q3 and state_counting_q;
pld_msel0<=(not state_error_q) and (not state_done_q);
pld_msel1<='0';
drive_outputs<=(not state_error_q) and (not state_done_q);
data0<=(data_bit_counter_cout and D(0))or((not data_bit_counter_cout)and shift_register_shiftout);
not_restart_sequence<=not restart_sequence;
not_reset_n<=not reset_n;
not_status_n<=not status_n;
not_reset_pulse_q<=not reset_pulse_q;
not_try_user_config_q<=not try_user_config_q;
not_config_n_reg_q<=not config_n_reg_q;
loading_led<=((state_counting_q and (not state_done_q)and (not state_error_q))and address_counter_q(16)) or reset_pulse_q;
user_led<=try_user_config_q and (not state_error_q);
error_led<=state_error_q;
--例化元件映射关系
u1 : dclk_divider port map(clock=>cpld_clkosc, aclr=>restart_sequence, q(3)=>dclk_divider_q3, cout=>dclk_divider_cout);
u2 : address_counter port map(clock=>cpld_clkosc, clk_en=>address_counter_clk_en, cnt_en=>state_counting_q, aclr=>restart_sequence, q=>address_counter_q, cout=>address_counter_cout);
u3 : data_bit_counter port map(clock=>cpld_clkosc, clk_en=>dclk_divider_cout, cnt_en=>state_counting_q, aclr=>restart_sequence, cout=>data_bit_counter_cout);
u4 : shift_register port map(clock=>cpld_clkosc, enable=>shift_register_enable, load=>data_bit_counter_cout, data(6 downto 0)=>D(7 downto 1), aclr=>restart_sequence, shiftout=>shift_register_shiftout);
u5 : dff port map(d=>not_reset_n, clk=>cpld_clkosc, clrn=>'1', prn=>reset_n, q=>reset_pulse_q);
u6 : dff port map(d=>try_user_config_d, clk=>cpld_clkosc, clrn=>'1', prn=>not_reset_n, q=>try_user_config_q);
u7 : dff port map(d=>eek_an_error_d, clk=>cpld_clkosc, clrn=>not_reset_pulse_q, prn=>'1', q=>eek_an_error_q);
u8 : dffe port map(d=>state_error_d, clk=>cpld_clkosc, ena=>dclk_divider_cout,clrn=>not_reset_pulse_q, prn=>'1', q=>state_error_q);
u9 : dff port map(d=>counter_wrapped_d, clk=>cpld_clkosc, clrn=>restart_sequence, prn=>'1', q=>counter_wrapped_q);
u10 : dffe port map(d=>not_status_n, clk=>cpld_clkosc, ena=>dclk_divider_cout, clrn=>not_restart_sequence, prn=>'1', q=>state_waiting_for_status_n_q);
u11 : dffe port map(d=>state_done_d, clk=>cpld_clkosc, ena=>dclk_divider_cout, clrn=>not_restart_sequence, prn=>'1', q=>state_done_q);
u12 : dffe port map(d=>state_counting_d, clk=>cpld_clkosc, ena=>dclk_divider_cout, clrn=>not_restart_sequence, prn=>'1', q=>state_counting_q);
u13 : dffe port map(d=>'1', clk=>cpld_clkosc, ena=>dclk_divider_cout, clrn=>not_restart_sequence, prn=>'1', q=>config_n_reg_q);
u14 : tri port map(a_in=>'1', oe=>drive_outputs, a_out=>flash_a22);
u15 : tri port map(a_in=>'1', oe=>drive_outputs, a_out=>flash_a21);
u16 : tri port map(a_in=>not_try_user_config_q, oe=>drive_outputs, a_out=>flash_a20);
u17 : tri port map(a_in=>address_counter_q(19), oe=>drive_outputs, a_out=>a(19));
u18 : tri port map(a_in=>address_counter_q(18), oe=>drive_outputs, a_out=>a(18));
u19 : tri port map(a_in=>address_counter_q(17), oe=>drive_outputs, a_out=>a(17));
u20 : tri port map(a_in=>address_counter_q(16), oe=>drive_outputs, a_out=>a(16));
u21 : tri port map(a_in=>address_counter_q(15), oe=>drive_outputs, a_out=>a(15));
u22 : tri port map(a_in=>address_counter_q(14), oe=>drive_outputs, a_out=>a(14));
u23 : tri port map(a_in=>address_counter_q(13), oe=>drive_outputs, a_out=>a(13));
u24 : tri port map(a_in=>address_counter_q(12), oe=>drive_outputs, a_out=>a(12));
u25 : tri port map(a_in=>address_counter_q(11), oe=>drive_outputs, a_out=>a(11));
u26 : tri port map(a_in=>address_counter_q(10), oe=>drive_outputs, a_out=>a(10));
u27 : tri port map(a_in=>address_counter_q(9), oe=>drive_outputs, a_out=>a(9));
u28 : tri port map(a_in=>address_counter_q(8), oe=>drive_outputs, a_out=>a(8));
u29 : tri port map(a_in=>address_counter_q(7), oe=>drive_outputs, a_out=>a(7));
u30 : tri port map(a_in=>address_counter_q(6), oe=>drive_outputs, a_out=>a(6));
u31 : tri port map(a_in=>address_counter_q(5), oe=>drive_outputs, a_out=>a(5));
u32 : tri port map(a_in=>address_counter_q(4), oe=>drive_outputs, a_out=>a(4));
u33 : tri port map(a_in=>address_counter_q(3), oe=>drive_outputs, a_out=>a(3));
u34 : tri port map(a_in=>address_counter_q(2), oe=>drive_outputs, a_out=>a(2));
u35 : tri port map(a_in=>address_counter_q(1), oe=>drive_outputs, a_out=>a(1));
u36 : tri port map(a_in=>address_counter_q(0), oe=>drive_outputs, a_out=>a(0));
u37 : tri port map(a_in=>'0', oe=>drive_outputs, a_out=>flash_cs_n);
u38 : tri port map(a_in=>'0', oe=>drive_outputs, a_out=>flash_oe_n);
u39 : tri port map(a_in=>'1', oe=>drive_outputs, a_out=>flash_rw_n);
u40 : tri port map(a_in=>dclkq3_stcntg, oe=>drive_outputs, a_out=>DCLK);
u41 : tri port map(a_in=>data0, oe=>drive_outputs, a_out=>pld_data0);
u42 : tri port map(a_in=>'0', oe=>not_config_n_reg_q, a_out=>config_n);
END ARCHITECTURE config;⌨️ 快捷键说明
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