pll.v

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench

/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///
/// File        : pll.v
/// Author      : Parthus Technologies PLC
/// Date	: Mon Feb 17 06:08:33 2003
/// Info	: Job No = 12364215
///_______________________________________________________________________
///
///        Copyright (c) 2002 Parthus Technologies PLC.
///
/// This code is confidential and proprietary product of Parthus. Any
/// unauthorized use, reproduction or transfer of this code is strictly
/// prohibited.
///_______________________________________________________________________
///
/// Description: This file contains a behavioural model of the pll 
///		 
///_______________________________________________________________________
///
///
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///
/// Module      :  xtop4215
/// Author      : Parthus Technologies PLC
///_______________________________________________________________________
///
///        Copyright (c) 2002 Parthus Technologies PLC.
///
/// This code is confidential and proprietary product of Parthus. Any
/// unauthorized use, reproduction or transfer of this code is strictly
/// prohibited.
///_______________________________________________________________________
///
/// Description: This module instantiates the behavioural model of the analog 
///		 pll core along with the behavioural model of the digital 
///		 support circuitry. 
///		 
///_______________________________________________________________________
///
/// Note1: this model does not support jitter on the reference
///        clock or any kind of frequency or phase upset on the
///        reference clock.
///        
/// Note2: The following equation governs the vco frequency :-
///        	vco_freq = (ref_freq/M)*N
///        ensure that IPD = M-1 and FBD = N-1
///        
/// Note3: The vco_freq can be varied by +/-25.000 percent of its nominal
///         	pfd_freq = ref_freq/M
///         The pfd_freq can be varied by +/-30.000 percent of its nominal
///        
/// Note4: the SETTLING_TIME has been shortened by one-tenth in order
///        to facilitate the fast turn around of several tests. Please
///        ensure that you use the correct SETTLING_TIME in the critical
///        applications
///        
///
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps      //the precision is specified as 1ps. This can be
			//decreased to a minimum of 100ps


module xtop4215
	   (porL, sleepL, refClk, forceBypass,
	    FBD0, FBD1, FBD2, FBD3, FBD4, FBD5, FBD6, FBD7,
	    IPD0, IPD1, IPD2, IPD3, IPD4, IPD5, IPD6, IPD7,
	    xClk01,
	    xClk02,
	    xClk03,
	    pllLock, sysResetL
);

input porL;
input sleepL;
input refClk;
input forceBypass;
input FBD0;
input FBD1;
input FBD2;
input FBD3;
input FBD4;
input FBD5;
input FBD6;
input FBD7;

input IPD0;
input IPD1;
input IPD2;
input IPD3;
input IPD4;
input IPD5;
input IPD6;
input IPD7;

output xClk01;
output xClk02;
output xClk03;

output pllLock;
output sysResetL;


wire divClk, vcoClk, fbClk, lockDetAsync;
wire [63:0] filterVoltageBus;

wire [7:0] FBD;
wire [7:0] IPD;

assign IPD[0] = IPD0;
assign IPD[1] = IPD1;
assign IPD[2] = IPD2;
assign IPD[3] = IPD3;
assign IPD[4] = IPD4;
assign IPD[5] = IPD5;
assign IPD[6] = IPD6;
assign IPD[7] = IPD7;

assign FBD[0] = FBD0;
assign FBD[1] = FBD1;
assign FBD[2] = FBD2;
assign FBD[3] = FBD3;
assign FBD[4] = FBD4;
assign FBD[5] = FBD5;
assign FBD[6] = FBD6;
assign FBD[7] = FBD7;


pllCore4215 IpllCore( .divClkin(divClk), .porL(porL), .sleepL(sleepL),
		  .FBD(FBD),
		  .VCODelayed(vcoClk),
                  .fbClk(fbClk), .lockDetAsync(lockDetAsync), .vcoClk(vcoClk),
                  .filterVoltageBus(filterVoltageBus));


pllDig4215 IpllDig (.porL(porL), .sleepL(sleepL), .lockDetAsync(lockDetAsync),
                .refClk(refClk), .vcoClk(vcoClk), .forceBypass(forceBypass),
                .divClk(divClk),
		.IPD(IPD),
		.xClk01(xClk01),
		.xClk02(xClk02),
		.xClk03(xClk03),
                .pllLock(pllLock), .sysResetL(sysResetL));


endmodule

/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///
/// Module      : pllDig
/// Author      : Parthus Technologies PLC
///_______________________________________________________________________
///
///        Copyright (c) 2002 Parthus Technologies PLC.
///
/// This code is confidential and proprietary product of Parthus. Any
/// unauthorized use, reproduction or transfer of this code is strictly
/// prohibited.
///_______________________________________________________________________
///
/// Description: This file contains a behavioural model of the digital  
/// 	         support circuitry for the analog pll core.
///
///		 
///_______________________________________________________________________
///
///
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

`define v4215init1 1
`define v4215start1 6
`define v4215hi1 4
`define v4215lo1 6

`define v4215init2 1
`define v4215start2 6
`define v4215hi2 6
`define v4215lo2 6

`define v4215init3 1
`define v4215start3 10
`define v4215hi3 8
`define v4215lo3 10


module pllDig4215 (porL, sleepL, lockDetAsync, refClk, vcoClk, forceBypass, divClk,
		  IPD,
		  xClk01,
		  xClk02,
		  xClk03,
		  pllLock, sysResetL);


input porL; 
input sleepL;
input lockDetAsync;
input refClk;        
input vcoClk; 
input forceBypass;       
input [7:0] IPD;

output xClk01;
output xClk02;
output xClk03;
output divClk;
output pllLock;    
output sysResetL;  


reg iDivClk;
reg [8:0] countIPD;
reg xClk01;
reg xClk02;
reg xClk03;

wire divClk;
wire IPDReset, clkResetL, intSleepL, intLockDetAsync, clkin;

assign intSleepL = forceBypass ? 1'b1 : sleepL;
assign intLockDetAsync = forceBypass ? 1'b1 : lockDetAsync;
assign clkin = forceBypass ? refClk : vcoClk;


resetBlock4215 iResetBlock (.porL(porL), .sleepL(intSleepL), 
                        .lockDetAsync(intLockDetAsync), 
                        .vcoClk(clkin), 
			.slowestClk(xClk03),
                        .refClk(refClk),
                        .pllLock(pllLock), .sysResetL(sysResetL), 
                        .IPDReset(IPDReset), .clkResetL(clkResetL));


initial iDivClk = 0;

always @(posedge IPDReset)
   begin
   @(posedge refClk or IPDReset);
   while(IPDReset)
      begin
      iDivClk = !iDivClk;
      repeat(IPD+1) @(refClk or IPDReset);
       iDivClk = !iDivClk;
       if(IPDReset)
         repeat(IPD+1) @(refClk or IPDReset);
      end
   end

assign divClk = (IPD==0) ? refClk : iDivClk;

initial xClk01 = `v4215init1;

always @(posedge clkResetL)
   begin
   xClk01 = `v4215init1;
     repeat(`v4215start1) @(clkin or clkResetL);
   while(clkResetL)
       begin
       xClk01 = !xClk01;
       repeat(`v4215hi1) @(clkin or clkResetL);
       xClk01 = !xClk01;
       if(clkResetL)
          repeat(`v4215lo1) @(clkin or clkResetL);
       end
     end

initial xClk02 = `v4215init2;

always @(posedge clkResetL)
   begin
   xClk02 = `v4215init2;
     repeat(`v4215start2) @(clkin or clkResetL);
   while(clkResetL)
       begin
       xClk02 = !xClk02;
       repeat(`v4215hi2) @(clkin or clkResetL);
       xClk02 = !xClk02;
       if(clkResetL)
          repeat(`v4215lo2) @(clkin or clkResetL);
       end
     end

initial xClk03 = `v4215init3;

always @(posedge clkResetL)
   begin
   xClk03 = `v4215init3;
     repeat(`v4215start3) @(clkin or clkResetL);
   while(clkResetL)
       begin
       xClk03 = !xClk03;
       repeat(`v4215hi3) @(clkin or clkResetL);
       xClk03 = !xClk03;
       if(clkResetL)
          repeat(`v4215lo3) @(clkin or clkResetL);
       end
     end


endmodule

module resetBlock4215 (porL, sleepL, lockDetAsync, vcoClk, slowestClk, refClk,
                   pllLock, sysResetL, IPDReset, clkResetL);


input porL; 
input sleepL;
input lockDetAsync;
input vcoClk;        
input slowestClk;        
input refClk;        

output pllLock;    
output sysResetL;    
output IPDReset;    
output clkResetL;  

reg IPDReset;
reg intIPDReset;

reg pllActive;
reg intPllActive1;
reg intPllActive2;

reg iClkResetL;
reg intClkResetL1;
reg intClkResetL2;

reg iPllLock;
reg intPllLock1;
reg intPllLock2;

reg iSysResetL;
reg intSysResetL1;
reg intSysResetL2;


wire iResetL;

initial
   begin
   IPDReset = 0;
   intIPDReset = 0;

   iClkResetL = 0;
   intClkResetL1 = 0;
   intClkResetL2 = 0;

   pllActive = 0;
   intPllActive1 = 0;
   intPllActive2 = 0;

   iPllLock = 0;
   intPllLock1 = 0;
   intPllLock2 = 0;

   iSysResetL = 0;
   intSysResetL1 = 0;
   intSysResetL2 = 0;
   end

//triple bank lockDetAsync

always @(posedge vcoClk or negedge iResetL) 
   if(!iResetL)
      begin
      intPllLock1 <= 1'b0;
      intPllLock2 <= 1'b0;   
      iPllLock <= 1'b0;
      end
   else
      begin
      intPllLock1 <= lockDetAsync;
      intPllLock2 <= intPllLock1;   
      iPllLock <= intPllLock2;
      end

//latch pllLock to form SysResetL 3 slowestClk cycles after pllLock 

always @(posedge slowestClk or negedge iResetL)	
   if(!iResetL)
      begin
      intSysResetL1 <= 1'b0;
      intSysResetL2 <= 1'b0;
      iSysResetL <= 1'b0;
      end
   else
      begin
      intSysResetL1 <= iPllLock;
      intSysResetL2 <= intSysResetL1;
      iSysResetL <= iSysResetL | intSysResetL2;
      end

//generate pllActive  

always @(posedge vcoClk or negedge iResetL)
   if(!iResetL)
      begin
      intPllActive1 <= 1'b0;
      intPllActive2 <= 1'b0;
      pllActive <= 1'b0;
      end
   else 
      begin
      intPllActive1 <= 1'b1;